DLA SMD-5962-95569-1995 MICROCIRCUIT DIGITAL 32-BIT EMBEDDED RISC MICROCPROCESSOR MONOLITIC SILICON《32-BIT植入的精简指令集计算机微型处理器硅单片电路线型微电路》.pdf

1、LTR DESCRIPT ION DATE (YR-M-DA) PMIC NIA APPROVED STANDARD MICROCIRCUIT DRAWING PREPARED BY Thomas M. Hess CHECKED BY Thomas M. Hess P APPROVED BY Monica L. Poelking DRAWING APPROVAL DATE 95-03-31 REVISION LEVEL THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF D

2、EFENSE DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 MICROCIRCUIT, DIGITAL, 32-BIT EMBEDDED RISC MICROPROCESSOR, MONOLITHIC SILICON SIZE CAGE CODE 5962-95569 A 67268 AMSC N/A SHEET 1 OF 28 I BC FORM 193 JUL 94 DISTRIBUTION STATEMENT A. Approved for pub1 ic release: distribution is unlimited.

3、5962-E156-95 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-W 999999b 0072297 345 _- SMD-5962-95569 , 1. SCOPE STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTW DAYTON, OHIO 45444 1.1 a. This drawing forms a part of a one part - one par

4、t number documentation system (see 6.6 herein). Two product assurance classes consisting of mllitary high reliability (device classes Q and M) and space application (device class V), and a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Nuher (PIN

5、). Device class M microcircuits represent non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883, “Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices“. When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. I SI

6、ZE 5962-95569 A REVISION LEVEL SHEET 2 I 1.2 m. The PIN shall be as shown in the following exanple: 5962 95569 o1 P Y X I I 1 II designator (see 1.2.1) (see 1.2.2) des igna tor (see 1.2.4) (see 1.2.5) - I i I I I I I I I 1 I Lead stock class designator type class outline finish Case Dev i ce Device

7、Federa 1 RHA LA (see 1.2.3) I Drawing number 1.2.1 RHA desisnator. Device class M RHA mrked devices shall meet the MIL-1-38535 appendix A specified RHA levels and shall be marked with the appropriate RHA designator. Device classes Q and V RHA marked devices shall meet the MIL-1-38535 specified RHA l

8、evels and shall be marked with the appropriate RHA designator. A dash (-1 indicates a non-RHA device. 1.2.2 Device tupe(s1. The device type(s) shall identify the circuit function as follows: Dev i ce type Generic number Circuit f unct ion o1 MG8096OMX 32-bi t superscalar microprocessor 1.2.3 Device

9、class desiqnator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Device reuuiremnts documentation M I Vendor self-certification to the requirements for non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STO-883 - Certi

10、fication and qualification to MIL-1-38535 - Q or V 1.2.4 Case outline(s1. The cae outline(s) shall be as designated in MIL-STD-1835 and as follows: I Outline letter Descriptive desisnator Termi na 1 s Y See figure 1 348 Packacie stvle Ceramic pin grid array Provided by IHSNot for ResaleNo reproducti

11、on or networking permitted without license from IHS-,-,-t SMD-5962-75569 = 9999996 0072298 081 , 1.3 Absolute maximum ratinqs. lJ Storage tenperature range Vc supply voltage with respect to ground range Vottage on any pin with respect to ground range Lead tenperature (soldering, 10 seconds) . Juncti

12、on temperature . Thermal resistance, junction-to-case (OJc): CaseY . Thermal res is tance, junct ion-to-aI ON LEVEL STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 F I I 1 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted wi

13、thout license from IHS-,-,-SHD-5962-955b7 m 77777b O072300 5bT m I TABLE I. Electrical performance characteristics. l Test STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I I I I SIZE 5962-95569 A REVISION LEVEL SHEET 5 Unit I -55C S TC S, t125OC I subgroups I type

14、 I I unless otherwise specified I I I Max 0.8 V Low level input voltage I VIH Frequency - 4 MHz I I I I 1,2,3 I All I 2.0 V vcc+o.3 High level input voltage I I I I I I I I I I I 1 I 1,2,3 I All I -0.3 VIL-RST 12/ Input low voltage reset 0.8 V I I I I I I I I I I I I 1,2,3 I All I 2.0 VIH-RST Ifrequ

15、ency = 4 MHz Input high voltage reset Vcc+O. 3 V Input low voltage clock-in I I I VCL 12/ I I I 1 I I I l I 1,2,3 I All I -0.3 0.8 V Input high voltage clock-in ucc V Output low voltage 0.45 V Output low voltage 0.45 V V - Output high voltage Voltage input ref. voltage 1.5 VIREF 10 I i 1,2,3 i All 1

16、 1.1 I I I V Power supply current 1.3 Icc I I i 1,2,3 i All i I I I A I 1 I I I I 1,2,3 1 All 1 I I ILI1 lo VIN vcc 5/ I I I I I 115 Input leakage current I I I I See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2

17、-955b9 = 999999b 0072303 4Tb = TABLE I. Electrical performance characteristics - Continued. I I I I Test Conditions I/ 1 Group A Device i Limits i Unit -55 5 T 5 +1250c i subgroups i type i unless otherwise specified I I I I i 4.75 V S VCC 5 5.25 V I ILI2 VIN = 0.45 V s/ i 1.2.3 1 All I I I I t400 I

18、 I Input leakage current Input 1 ea kage current ILI3 IL0 Output leakage current Capacitance on input pins IN Capacf tance on BBUS address and control BA Func t iona 1 test See 4.4.lb Jperating frequency LJcc = 4.75 v i i tl LJcc = 4.75 v See figure 4 I I I I I I 9,10,11 I All I 50 l I I I I I ns I

19、I Clock period I t See figure 4 I I I I I VIL = 10% point s/ I 9,10,11 I All I 12.5 I I “S I I I I I See figure 4 l I I I I JIH - 90% point 9J I 9.10.11 1 All 1 12.5 1 I ns I I I I I t2 - Clock low time - :lock high time t3 I I I I I See figure 4 I I I I I t4 dIN = 90% to 10% pointg/u/ i 9.10.11 i A

20、I i 1 12.5 i ns I I 1 I I I I I Jcc = 4.75 v I I :lock fall time See figure 4 I I I I I vIN - 90% to 10% pointg/ll/ i 9.i0.11 i AII i i 12.5 j ns ! ! ! ! ! vcc - 4.75 v :lock rise time I I I I I See figure 4 I I I I I Ellys/ 1 9,10,11 I All 1 25 I I ns I l I I I teset set-up t6 See footnotes at end

21、of table. -!- REVISION LEVEL STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 5962-95569 SHEET 6 JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-l I I I I STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPP

22、LY CENTER DAYTON, OHIO 45444 SIZE 5962-95569 A REVISION LEVEL SHEET 7 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-I I I I I Test I sm1 i t20 1 91 6-Bus addr. and control output val id I Lclkout output val id I PFail output vaild STANDARD MICROCIR

23、CUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I I LError (1:O) output valid I t23 SIZE 5962-95569 A REVISION LEVEL SHEET a I l I t24 Open drain output valid I I I i t26 I I I t27 I I Open drain input Set-up I t25 Open drain input hold Bstopbus input Set-up I 1 %!8 I I t29 I Bstop

24、bus input hold Hisc. signal input Set-up I I I t30 Misc. signal input hold I 1 t31 8-Bus float delay output val id I I I t32 nLBus float delay See footnotes at end of table. Conditions I/ -55C 5 TC S t125“C 4.75 V 5 Vcc S 5.25 V unless otherwise specified 25 - 4.75 “ See figure 4 I = 4.75 v Ql3J jee

25、 figure 4 I-; = 4.75 jee figure 4 Iss = 4.75 Se figure 4 I,“ = 4.75 v Group A subgroups 9.10.11 9,10,11 9,10,11 9,10,11 9,10,11 9,10,11 9,10,11 9.10.11 9,10,11 9,10,11 9,10,11 9,10,11 9,10.11 Devi ce type Al 1 Al 1 Al 1 Al 1 Ai 1 Al 1 Al 1 Al 1 Al 1 Al 1 Al 1 Al 1 Al 1 I Limits I Unit I - I I I I I

26、I 1 10 I ns 25 I 37 I nc I I Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-95569 9999996 0072304 LO5 STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CWTW DAYTON, OHIO 45444 TABLE I. Electrical performance characteristics - Continu

27、ed. I/ All testing to be performed using worst-case test conditions unless otherwise specified. 21 VIL min - -0.3 V for a pulse width of less than 20 ns. - 3/ The I s igna?klnat covered by IoL1, i/ VIgnewref is held at 1.5 V for ac testing. s/ Pins with no pull-up or pull down resistor. 61 These pin

28、s have internal pull-up resistors (init 8:O). 7J These plns have internal pull-down resistors (Clksel). s/ Tested at Vcc = 5.25 V. 9/ Tested at Vcc = 4.75 V. o/ For ac testing clock rise and fall times are typically 3 ns. y Guaranteed by design, not tested. 12/ These signals are either sampled or dr

29、iven on the negative edge of the internal processor clock which is independent of CLKin duty cycles (always 50 percent duty cycle internally). rating pertains to all signals covered under T17 and TZ4. The IOLZ rating pertains to the rest of the u/ CL = 50 pF. o/ Float condition occurs when maximum o

30、utput current falls below IoL in Mgnitude. _ SIZE 5962-95569 A REVISION LEVEL SHEET 9 JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-1- SMD-5962-955b9 W 999999b 0072305 041 Case Y Note: I/ The US government preferred system of measurement is

31、the metric SI system. However, this item was originally designed using inch-pound units of measurement. units the inch-pound units shall take precedence. In the event of conflict between the metric and the inch-pound BASE PLANE STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON,

32、OHIO 45444 SIZE 5962-95569 A REVISION LEVEL SHEET 10 FIGURE 1. Case outline. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-9999996 007230b T88 W I Devi ce type Case outline o1 Y STANDARD MICROCIRCULT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON

33、, OHIO 45444 SIZE 5962-95569 A REVISION LEVEL SHEET 11 outltne Iy :ase iutl ine ermi na 1 Termi na 1 iler 1pWl Terminal Terminal nwr 1s- Terminal Terminai dr Isyrtmi AH04 I BADOR12 AJ23 I LADO101 I AL09 I Vss 1 BWRACC BWRICYC “ss AL13 vss AL11 I AJ33 I LsT21 I LADDT15 LADDT16 AL19 Vss I AL23 1 VSS I

34、 AH24 I LADDT06 1 Et I BOATA28 11 AEO1 1 Vcc BDATA22 AE03 BDIRSTO BOATA25 AE05 BAwR13 A129 I Vss I BMISS * LADOT25 1 :2: 1 DATA26 11 A: 1 LUl.7 A33 EDATA30 AE37 LAODT23 BOATA29 I vss AL35 I LAWTO7 I Ni: 1 LADDT19 BADDR03 AJO3 BADDR17 AL37 I LADDT11 I A35 BOATA21 A37 BDATA18 AA01 I AF34 1 LADOT30 AK2

35、4 LADDTP1 AK26 LADDTT 1 AA03 Vss (I AF36 I Vcc AA05 EADDR18 AGO1 EDIRTAG28 Mi: I mE BNEWBLK AKN: I MN LMEMPTYQ AM1 o AH1 2 AM14 “cc AM16 LSIZEBYTEO AK32 I LADOT04 AA35 LADOTOB AK 34 AK36 LADOT12 LACCi2 LVAL I 0 ALOI NC EADDR 19 LADDTZO AL03 I BADOR10 1 FIGURE 2. Terminal connections. Provided by IHS

36、Not for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 SIZE 5962-95569 A REVISION LEVEL SHEET 12 I O1 kvice type I O1 Devi ce type kv i ce Devi ce sutline outline rerminal $ Terminal outlin

37、e I E07 I BTRISTATE I ipi 1 BDATATO BDATA03 BDATA07 I BO8 vcc E10 vcc E1 2 vcc E16 vcc E18 vcc E20 vcc E22 vcc E14 BOATA11 C31 vcc EIRP3 E21 BATA31 GO3 EIRP1 EDATA38 DO2 BDIRPO DO4 I E24 I vcc DO6 I EDATAPO E25 I BDATA39 II 633 I VCC 1 I vcc DO8 I BDATAOP q-+ 832 BDATAP4 BDATA56 BIRP4 BDATA45 H34 ED

38、ATA57 BDATA46 H36 vcc E34 BDATAP5 E36 MATA33 D16 vss Dl8 F04 I Vss II JO3 I BIRTAC16 I I vcc 12; 1 EDATAT1 EDATA36 028 EDATA43 53) I BDIRP5 I :(I: I CLKIN CLKVqq BDATA61 + BDATA55 BDATA04 BDATAO8 F16 I BDATA15 I C15 vcc BDATA4 1 BDIRPZ F18 I BDATA23 11 K34 I BDATAG;. I F20 I BDATAP3 II K36 I VCC I -

39、=+- CLKSEL E-: I :i 11 :(It I EDIRTAG17 1 EDIRTAGZO FIGURE 2. Terminal connections - Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-955bq b 0032308 850 D lev i ce o1 Devi ce type type :ase Y Case wtline outline Terminal Terminal

40、Terminal number sm1 nunter w33 TO4 BDIRTAG30 u35 T34 INIT1 u37 TO2 vss o1 Y Terminal sml XINT5 - vss - IAC L35 “ss STANDARD SIZE MICROCIRCUIT DRAWING A DAYTON, OHIO 45444 REVISION LEVEL DEFENSE ELECTRONICS SUPPLY CENTER 5962-95569 SHEET 13 17 Devi ce Y Iy :ase )ut1 ine Termina 1 nuhr Termi na 1 s-1

41、BDIRTAG19 ICEMSG/ IN IT8 - LO5 L33 BDIRTAG25 Qo3 I vss 405 I IRTAG24 433 I INIT +P- INIT6 BOIRTAGZZ INIT7 I M36 I vcc R02 I vcc BD IRTAG26 INITQ NO5 BD IRTAG23 I N33 I INIT4 I+ PFAIL SO3 SO5 BDIRTAG27 - XINT1 BADDR22 XI NT4 WO5 BADDR24 236 =-P- INITS BDIRTAGZ1 INIT3 FIGURE 2. Terminal connections -

42、Continued. DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SUD-5962-95569 D 9999996 0072309 797 - 41 I .* I r IaM BIIS IDWDATA BACKSIDE Bus Bus COt(TR0LLER DATA I FLOATINI, POINT I INTERRUPT * CONTROL UNIT WSUB UNIT 1 r 1 I - XI

43、NTO- NHI XIUT7 - I INTBER MLTIPL/OIPIDE UNIT 1 I FLOATIN6 WIN1 WLTIPLVDIVIDE UNIT EXECUTION LOGICAL INSTRUCTION SCHEDU WOECODER Itt r- INTEiER EXECUTIOW UNIT 1 I EHORI IIANAGMOIT UNIT I LOW REGISTER CACHE I8 SETSI FIGURE 3. Block diaqram. TRAWSLATION LOOKASIDE BUFFER 1 PHTSICU. Aw#IEss r 4 DATA it K

44、BTEI L STANDARD 5962-95569 MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CWTW DAYTON, OHIO 45444 REVISION LEVEL SHEET DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-95569 HIGH LEVEL MIN C 2.0 v kin 1.5 v 10% W 999999

45、6 0072330 409 Lr LOU LEVEL MAXI O. 8 V Clock Pulse BTr iState 1.5 v I I INIT (11 1.5 V II AC Timing for Resetlx mode) FIGURE 4. Timincl waveforms. STANDARD 5962-95569 MICROCIRCUIT DRAWNG DEFENSE ELECTRONICS SUPPLY CENTW DAYTON, OHIO 45444 REVISION LEVEL SHEET DESC FORM 193A JUL 94 Provided by IHSNot

46、 for ResaleNo reproduction or networking permitted without license from IHS-,-,-Cllcin ilx mode) nLBur Outputs SEE NOTE 1 niBus Output Cont ro I L 1.5 V VALID OUTPUT(n*lt I I -I 1.5 V VALID OUTPUT(n+lt VAL ID SEE NOTE 2 OUTPUT nwi/h LC 1 k Out Output 1.5 V VALID OUTPUT(n+ll LVa 1 id. VAL ID LNeuBIk

47、OUTPUT n outputs 1.5 V VALID OUTPUT(n+l) nL6us Output S Lgna 1 s Clkin (lx model 1.5 V nLBus Inputs VALID SEE NOTE 1 nLBus Dtd. At15+ I SEE NOTE 2 Inputs VALID - LVa 1 id, Inputs LNeiBIY nLBus Input Signals 16 KCV 131UiY LCVLL I JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permi

48、tted without license from IHS-,-,-Clkin (lx model - STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 B-Bus Data and Dir Outputs SEE NOTE 2 5962-95569 SIZE A REVISION LEVEL SHEET 17 B-Bus Addr and Cntl Outputs SEE NOTE 1 I VALID VALID SMD-5762-95569 = 9979796 0072332 281 H - PFail Output Cltin (lx model B-Bus Data and Dir Inputs SEE NOTE 1 BStopBus Input 1.5 V VALID h+ll VALID VALID OUTPUT n B-Bus Output Signals 6-Bus Input Signals FIGURE 4. Timinq waveforms - Continued. DES