DLA SMD-5962-95576 REV A-1996 MICROCIRCUIT DIGITAL ADVANCED BIPOLAR CMOS 36-BIT UNIVERSAL BUS TRANSCEIVER WITH THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS MONOLITHIC SILICON《先进双极互补金属.pdf

1、SMD-5962-9557b REV A m 9999996 0088237 O12 m DEFENSE LOGISTICS AGENCY DEFENSE ELECTRONICS SUPPLY CENTER 1507 WILMINGTON PIKE DAYTON, OH 45444-5765 IN REPLY REFER TO: DESC-ELDC (Mr. Kerby/(DSN)986-6023/5 13-296-6023hjj) JUN 11 SUBJECT: Notice o Revision (NOR) 5962-R13 1-96 or Standard Microcircuit Dr

2、awing (SMD) 5962-95576 Militaryhdustry Distribution The enclosed NOR is approved for use effective as of the date of the NOR. In accordance with MIL-STD- 100 SMD holders should, as a minimum, handwrite those changes described in the NOR to sheet 1 of the subject SMD. After completion, the NOR should

3、 be attached to the subject SMD for future reference. Those companies who were listed as approved sources of supply prior to this action have agreed to actions taken on devices for which they had previously provided DESC a certificate of compliance. This is evidenced by an existing active current ce

4、rtificate of compliance on file at DESC with a DESC record of verbal coordination. The certificate of compliance for these devices is considered concurrence with the new revision unless DESC is otherwise notified. If you have comments or questions, please contact Joe Kerby at (DSN)986-6023/(5 13)296

5、-6023. 1 Encl MONICA L. POELKING Microelectronics Branch add IlAta. Revisions description colum; add “Changes in accordance with NOR 5962-R131-96I8. Revisions date colum; add l196-O5-22l1. Revision level block; add I1AI1. Rev status of sheets; for sheets 1, and 5, add arA81. 3.5 Marking; delete and

6、replace as follows: “The part shall be marked with the PIN listed in 1.2 herein. Marking for device class M shall be in accordance with MIL-STD-883 (see 3.1 herein). In addition, the manufacturers PIN may also be marked as listed in MIL-BUL-103. be in accordance with MIL-PRF-38535. For class N devic

7、es only, the date code format may be modified as a traceable date code in lieu of the inspection lot date code for case outline XII. Revision level block; add llA1l. Marking for device classes N, CI, and V shall DESC-ELDC d. TITLE Acting Chief, Custom Microelectronics 15a. ACTIVITY ACCOMPLISHING REV

8、ISION DESC-ELDC DD Form 1695, APR 92 Prewous editions are obsolete. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-DESCRIPTION LTR SHEET I DATE (YR-MO-DA) APPROVED REV 111 REV STATUS OF SHEETS PMIC NIA STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS A

9、VAILABLE FOR USE BY ALL DEPARTRENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AHSC NIA JUL 94 PREPARED BY Joseph A. Kerby CHECKED BY Thanh V. Nguyen APPROVED BY Honica L. Poelking DRAWING APPROVAL DATE 95-04-06 REVISION LEVEL DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 MICROCIRCUIT, DIGITAL

10、, ADVANCED BIPOLAR CMOS, 36-BIT UNIVERSAL BUS TRANSCEIVER WITH THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON I I SIZE I CASE7iE I 5962-95576 A SHEET 1 OF 21 5962-E122-95 DISTRIBUTION STATEHLI4T A. Approved for public release; distribution 10 unlimited. Provided by IHSNot for ResaleN

11、o reproduction or networking permitted without license from IHS-,-,-5qb2-75576 W b 0072725 563 1.1 Scopc. This drawing forms a part of a one part - one part number documentation system (see 6.6 herein). Three product assurance classes consisting of space application (device class VI, mi litary high

12、reliabi lity (device classes fl and QI, and non-traditional military (device class N) with a choice of case outlines and lead finishes are available and are reflected in the Fart or Identifying Number (PIN). microcircuits in accordance with 1.2.1 of HIL-STD-883, “Provisions for the use of MIL-STD-88

13、3 in conjunction with compliant non-JAN devices“. the application environment. the FIN. Device class M microcircuits represent non-JAN class B For device class N, the user is cautioned to assure that the device is appropriate for When available, a choice of Radiation Hardness Assurance (RHA) levels

14、are reflected in 1.2 E. The FLN shall be as shown in the following example: - I I I I 5962 95576 T I T I T I Lead Case Devi ce Devi ce II Federal RHA stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number

15、1.2.1 RHA desianator. Device class M RHA marked devices shall meet the MIL-1-38535 appendix A specified RHA levels Device classes N, Q, and V RHA marked devices shall meet the and shall be mrked with the appropriate RHA designator. MIL-1-38535 specified RHA levels and shall be marked with the approp

16、riate RHA designator. non-RHA device. A dash (-1 indicates a 1.2.2 Device typeCs). The device typeCs) shall identify the circuit function as follows: Device type Generic number Circuit function o1 54ABT32501 36-bit universal bus transceiver with three-state outputs 1.2.3 Device class designator. The

17、 device class designator shall be a single letter identifying the product assurance level as follows: Device class Device rcguirernents documentation H N Vendor self-certification to the requirements for non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883 Certification and qualific

18、ation to MIL-1-38535 with a non-traditional performance environment I/ Q or V Certification and qualification to HIL-1-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: utline letter Descriptive desiqnator Terminals Package style X See figure 1 1

19、00 Plastic thin quad f tat package The lead finish shall be as specified in MIL-STD-883 (see 3.1 herein) for class H or 1.2.5 Lead finish. MIL-1-38535 for classes Q and V. designation is for use in Specifications when lead finishes A, 6, and C are considered acceptable and interchangeable without pr

20、eference. Finish letter “X“ shall not be marked on the microcircuit or its packaging. The “X“ For device class N, lead finish shall be in accordance with 1.2.5.1 herein. - I/ Any device outside the traditional performance environment; i.e., an operating temperature range of -55C to +125OC and which

21、requires hermetic packaging. I STANDARD 5962-95576 MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SID-57b2-75576 b 007272b YTT M _ 1.2.5.1 Lead finish D.

22、 Lead finish D shall be designated by a single letter as follows: STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 Finish Letter D SIZE A 5962-95576 REVISION LEVEL SHEET 3 Process Pa 1 ladi um 1.3 Absolute maximum ratinss. !/ 2/ I/ Supply voltaye range (V c) . DC in

23、put voltage range Fexcept I/O ports) (vIN) . DC output clamp current Thermal resistance, junction-to-case (OJc) . Junction temperature (lJ) . Maximum power dissipation at TA = +5SC (in still air) (PD) 1.4 Recommended nperatina conditions. 2/ 31 Supply voltage range (Vc 1 . Output vottaye range (Vwr)

24、 input voltage range : 2.0 V, niOEAB S 0.8 V - 10 VOUT = 2.7 V - -10 niO 2 2.0 V, niOEAB 5 0.8 V VOUT = 0.5 v - 50 For output under test Outputs at high logic state Vour = 5.5 v VOUT = 2.5 V -50 - -180 mA - 1 For input under test, VIN = 3.4 V For alt other inputs VIN = VCc or GND I Provided by IHSNo

25、t for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-95576 = 9999996 0072730 920 = . _. Group A Limits A/ Unit I ICCL 4.5 15.0 820 -1220 1810 -630 pF pF mV mV TABLE I. Electrical performance characteristics - Continued. I Test conditions 2/ -55OC 5 TC 5 t125C +4.

26、5 v 5 vcc 5 6.5 v unless otherwise specified Symbo 1 Test and test method If MIL-STD-883 Quiescent supply current, outputs high 3005 vcc subgroups - 3/ Min ICCH For ell inputs, VIN = VCc or GND IOUT = O A 5.5 v 1, 2, 3 Quiescent supply current, outputs low 3005 1, 2, 3 5.5 v - 5.5 v - 5.0 v - 5.0 V

27、- 5.0 v - 5.0 v 5.0 v - 5.0 v z- Quiescent supply current, outputs disabled Mo5 Input capacitance 301 2 ICCZ IN TC = +2SC See 4.4.lb Control inputs If0 capacitance 301 2 CIfO $- I V TiH= +25“C See 4.4.?d See figure 5 = 3.0 V, VIL 0.0 V Low level ground bounce noise voLP voLv Of High level Vcc bounce

28、 noise OHP 9 OHV 2 41 F unct iona 1 test 7 ifIH = 2.0 V, VIL = 0.8 V Verify output vo See 4.4.1 4.5 v 5.5 v 4.5 v and 5.5 v 4.5 v and 5.5 v - - - tL = 50 pF minimum, RL = SOOR See figure 6 Pulse duration, DiLEAB or niLEBA high ?, 10, 11 3.5 - 3.5 ?, IO, 11 tw2 tSl Puke duration, mCLKAB or DiCLKBA hi

29、gh or low Setup time, mAn or mn before mcLKABt or mCLKBAt See footnotes at end of table. 4.5 v and 5.5 v - STANDARD 5962-95576 MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I I I DESC FORM 193A SUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted wi

30、thout license from IHS-,-,-SMD-5962-95576 9999996 0072733 867 I STANDAR 5962-95576 MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 TABLE 1. Electrice1 performance characteristics - Continued. Limits $/ Symbol Group A subgroups Unit ns MHz - ns - ns ns - ns - ns - no Test co

31、nditions 2/ -55OC C TC i +125OC t4.5 v i vcc s +5.5 v unless otherwise specified CL = 50 pF minimum, RL = 50051 See figure 6 vcc 4.5 v and 5.5 v Test and test method I/ HIL-STD-883 Setup ti me, mAn or mn before mLEAa or mLEAJ Hold time, mAn or mn after. mCLKABT or mCLKOAf Min Max 9, IO, 11 2.5 ts2 4

32、.5 v and 5.5 v 9, 10, 11 thl Hold ti me, nAn or nBn after mLEAa or mLEBu th2 9, IO, 11 4.5 v and 5.5 v 4.5 v and 5.5 v 4.5 v and 5.5 v 4.5 v and 5.5 v Maximum operating frequency MAX 9, IO, 11 1 - 0.5 - 5.2 Propagation delay time, mAn or ai8n to rBn or inAn 3003 t 9, IO, 11 - O. 5 - 5.8 t 9, IO, 11

33、- 0.7 - 5.7 Propagation delay time, mLEAB or miEBA to mBn or mAn 3003 PLH2 4.5 v and 5.5 v 4.5 v and 5.5 v - 9, IO, 11 - 0.7 5.9 PHU 9, IO, 11 - 0.5 - 5.7 Propagation delay time, oCLKAB or nCLKA to mBn or nAn 3003 9, IO, 11 4.5 v and 5.5 v 4.5 v and 5.5 v 4.5 v and 5.5 v 4.5 v and 5.5 v - - _ 9, IO,

34、 11 0.7 5.8 tPHL3 - 0.5 - 6.2 Propagation delay time, output tnsbh oscilloscope with a 5M input impedance. The device inputs shall be conditioned such that all outputs are at a high nominal VoH level. The device inputs shall then be conditioned such that they switch simultaneously and the output und

35、er test remains at V other outputs possible are switched from VoH to VOL: Vm and VoHp are then measured from the nomina?“VoH level to the largest negative and positive peaks, respectively !see figure 5). This is then repeated with the same outputs not under test switching from Vol to Vw. The device

36、inputs shall be conaitioned such that all outputs arc at a low nomnal VOL le,rl. shall then be conditioned such that they switch simltaneously and the output under test remains at V other outputs possible are switched from VOL to Vw. VoLp and VOL“ are then measured from the nominaPLVoL level to the

37、largest positive aiid negative peaks, respectively (see figure 5). outputs not under test switching from VoH to VOL. Tests shall be performed in sequence, attributes data only. other logic patterns used for fault detection. minimum, test all functions of each input and output. shall be guaranteed, i

38、f not tested, to the truth table in figure 2 herein. in squence as approved by the qualifying activity on qualified devices. tolerances per flIL-STD-883, VIL = 0.4 V and VIH = 2.4 V. Output terminals not designated shall be high level logic, low level logic, or open, When performing these tests, the

39、 and AIcc tests, where the output terminals shall be open. For input terminals Production testing is performed at maximum operating This test may be performed either one input at a time (preferred method) or with all input pins = Vcc - 2.1 V (alternate method). Uhen the test is performed using the a

40、lternate test Ground and V bounce tests are performed on a non-switching (quiescent) The low and high level grwnd and Vcc bounce noise is measured at the quiet output as all The device inputs as all This is then repeated with the same Functional tests shall include the truth table and All possible i

41、nput to output logic patterns per function Functional tests shall be performed The test vectors used to verify the truth table shall, at a After incorporating allowable For outputs, L d 0.8 V, H 2 2.0 V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-

42、,-SMD-5962-95576 9 9999996 0072733 63T D + O 1 O0 50 LE 25 II 1 b SEE , DETAIL A l i A2 FIGURE l. Case outline. STANDARD 5962-95576 MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I I I DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitt

43、ed without license from IHS-,-,-SflD-59b2-75576 9999976 0072734 576 !/ Al1 dimensions are in milliicters. lhe top package body size my be smaller than the bottom package body sire by as much as 0.15.n. i/ Dimensions GI aiid EI do not include mold protrusion. are maximum plastic body size dimensions

44、including mold mismatch. i/ Dimension b docs not include dambar protrusion. to exceed the maximum b dimension by more than 0.08mn. the foot. !/ These dimensions apply to the flat section of the lead. Allowable protrusion is 0.25rm per side. DI and El Allowable dambar protrusion shall not cause the l

45、ead width Dambar can not be located on the louer radius or Ninimum space between protrusion and an adjacent lead is 0.07nm. FIGURE 1. Case outline - Continued. STANDARD 5962-95576 MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I I I DESC FORM 193A 1 JUL 94 Provided by IHSN

46、ot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-95576 9999996 0072735 402 SIZE A STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL Device type 5962-95576 SHEET 12 Case out Li ne Terminal number 1 2 3 .4 5 6 7

47、8 9 10 11 12 13 14 15 16 I7 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 o1 Terminal symbol 2A10 2A9 GND 2A8 2A7 2A6 2A5 GND 2A4 2A3 2A2 2A1 :Fi IA.? 1 A3 1 A4 GND 1 A5 1 A6 1 A7 1 A8 GND 1 A9 IA10 IA11 IA12 IA13 GND IA14 IA1 5 IA16 IA17 10EBA 1

48、LEBA 1 CLKBA I= 1 :L%B 1 LEA0 1 OEAB 1818 1817 1816 1815 1814 GND 1813 1812 1811 X Terminal number 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 IDO Terminal symbol . FIGURE 2. Terminal connections.

49、1810 1 89 GND 188 1 87 186 185 GND 184 183 182 1 E1 z55 202 283 204 GND 205 2B6 287 268 GND 289 281 o 281 1 281 2 281 3 GND 2014 201 5 2816 2817 2818 20eab 21eab 2CLKAB 2cLs$A 20eba 2A18 2A17 2A16 za15 2A14 GND 2A13 2A12 2A11 2- JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Pi