DLA SMD-5962-95587 REV B-2008 MICROCIRCUIT MEMORY DIGITAL CMOS ELECTRICALLY ERASABLE PROGRAMMABLE LOGIC DEVICE MONOLITHIC SILICON《单片硅点可擦可编程逻辑装置CMOS数字存储器微电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements. Editorial changes throughout. - gap 02-05-03 Raymond Monnin B Boilerplate update, part of 5 year review. ksr 08-07-16 Robert M. Heber REV SHET REV B B B SHEET 15 16 17 REV STATUS REV B B B B B B B B B B B B

2、 B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Michael Frye

3、AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 96-04-23 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, ELECTRICALLY ERASABLE PROGRAMMABLE LOGIC DEVICE, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-95587 SHEET 1 OF 17 DSCC FORM 2233 APR 97 5962-E459-08 Provided by I

4、HSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95587 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assuranc

5、e class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels ar

6、e reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 95587 01 Q X X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA desig

7、nator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) in

8、dicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Toggle speed (MHz) 01 ispLSI1048C EECMOS 8,000 gate in-system 50 programmable logic device 1.2.3 Device class designator. The device class designat

9、or is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification an

10、d qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA6-P133 133 Pin grid array 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device c

11、lasses Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95587 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FOR

12、M 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc Input voltage range (applied) -2.5 V dc to VCC+ 1.0 V dc Off state output voltage range applied -2.5 V dc to VCC+ 1.0 V dc Maximum power dissipation . 2.4 W 2/ Lead temperature (soldering, 10 seconds) +3

13、00C Thermal resistance, junction-to-case (JC): Case outline X See MIL-STD-1835 Junction temperature (TJ) . +175C 3/ Endurance 1000 erase/write cycles (minimum) Data retention (at +55C) . 20 years (minimum) 1.4 Recommended operating conditions. Case operating temperature range (TC) . -55C to +125C Su

14、pply voltage range +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) . 0 V dc Input high voltage (VIH) . 2.0 V dc to VCC+1.0 V dc Input low voltage (VIL) . 0.0 V dc to 0.8 V dc 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, stan

15、dards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification fo

16、r. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of

17、these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specifie

18、d herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation. ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevar

19、d, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 1/ Stresses above the

20、 absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Must withstand the added PDdue to short circuit test (e.g., IOS). 3/ Maximum junction temperature shall not be exceeded except for allowable

21、short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95587 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISI

22、ON LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific ex

23、emption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan sha

24、ll not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, constructi

25、on, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections sha

26、ll be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in screening (see 4.2 herein),

27、 or qualification conformance inspection groups A, B, C, or D (see 4.3 herein), the devices shall be programmed by the manufacturer prior to test. 3.2.3.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.2.4 Functional block diag

28、ram. The functional block diagram shall be as specified on figure 3. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and sha

29、ll apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 h

30、erein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still

31、be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL

32、-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this dra

33、wing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply

34、 for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for

35、device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) invo

36、lving devices acquired to this drawing is required for any change that affects this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95587 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVI

37、SION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available on

38、shore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, appendix A). 3.11 Processing of EEPLDs. All testing requirements and quality assurance provisions he

39、rein shall be satisfied by the manufacturer prior to delivery. 3.11.1 Conditions of the supplied devices. Devices will be supplied in cleared state per truth table in figure 2. No provision will be made for supplying written devices. 3.11.2 Writing of EEPLDs. When specified, devices shall be written

40、 in accordance with the procedures and characteristics specified in 4.6. 3.11.3 Clearing of EEPLDs. When specified, devices shall be cleared in accordance with the procedures and characteristics specified in 4.7. 3.11.4 Verification of state of EEPLDs. When specified, devices shall be verified as ei

41、ther written to the specified pattern or cleared. As a minimum, verification shall consist of performing a read of the entire array to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure and the device shall be remove

42、d from the lot or sample. 3.12 Endurance. A reprogrammability test shall be completed as part of the vendors reliability monitor. This reprogrammability test shall be done for initial characterization and after any design or process changes which may affect the reprogrammability of the device. The m

43、ethods and procedures may be vendor specific, but will guarantee the number of program/erase endurance cycles listed in section 1.3 herein. The vendors procedure shall be under document control and shall be made available upon request. 3.13 Data retention. A data retention stress test shall be compl

44、eted as part of the vendors reliability process. This test shall be done initially and after any design or process change which may affect data retention. The methods and procedures may be vendor specific, but will guarantee the number of years listed in section 1.3 herein. The vendors procedure sha

45、ll be under document control and shall be made available upon request. Data retention capability shall be guaranteed over the full military temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-9

46、5587 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Min Max Units Low level output voltag

47、e VOLIOL= 8.0 mA, VIL= 0.8 V, VCC= 4.5 V 1, 2, 3 0.4 V High level output voltage VOHIOH= -4.0 mA, VIL= 0.8 V, VCC= 4.5 V 1, 2, 3 2.4 V High level input voltage VIH1/ 1, 2, 3 2.0 V Low level input voltage VIL1/ 1, 2, 3 0.8 V Input or I/O low leakage current IIL0 V VIN 0.8 V 1, 2, 3 -10 A Input or I/O

48、 high leakage current IIH3.5 V VIN VCC1, 2, 3 10 A I/O active pull-up current 2/ IPU0 V VIN VIL1, 2, 3 -150 A Output short circuit current 3/ IOSVOUT= 0.5 V, VCC= 5.0 V, TA= +25C 1 -60 -200 mA Operating power supply current 4/ ICCVIL= 0.5 V, VIH= 3.0 V, f = 1.0 MHz 1, 2, 3 260 mA Dedicated input capacitance CINVIN= 2.0 V, VCC= 5.0 V, TA= +25C, f = 1.0 MHz, see 4.4.1e 4 10 pF I/O and clock capacitance CI/O, CYVI/O, VY= 2.0 V, VCC= 5.0 V, TA= +25C, f = 1.0 MHz, see 4.4.1e 4 10 pF Functional tests See 4.4.1c 7, 8A, 8B Data propagation delay, 4PT bypass, ORB bypass tPD19, 10, 11 22 ns Data prop