DLA SMD-5962-95593 REV A-2009 MICROCIRCUIT LINEAR 12-BIT 1 MHZ 75 MW A D CONVERTER W INPUT MULTIPLEXER AND SAMPLE HOLD MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Redraw. Update drawing to current requirements. drw 09-12-11 Charles F. Saffle REV SHET REV SHET REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Sandra Rooney DEFENSE SUPPLY CENTER

2、COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Sandra Rooney APPROVED BY Michael A. Frye MICROCIRCUIT, LINEAR, 12-BIT, 1 MHZ, 75 MW, A/D CONVERTER W/INPU

3、T MULTIPLEXER AND SAMPLE/HOLD, MONOLITHIC SILICON DRAWING APPROVAL DATE 95-03-21 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-95593 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E086-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MIC

4、ROCIRCUIT DRAWING SIZE A 5962-95593 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (dev

5、ice class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 95593 01 Q X

6、 A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and a

7、re marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type. The device type identifies the circuit function as fo

8、llows: Device type Generic number Circuit function 01 ADC12062 12-bit, 1 MHz, 75 mW, A/D converter with input multiplexer and sample/hold 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements

9、 documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline. The case outline is as designated in MIL-STD-1835 and

10、 as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 44 Quad flatpack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or n

11、etworking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95593 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/, 2/ Supply voltage (VCC= DVCC= AVCC) -0.3 V to +6 V Voltage at any

12、 input or output -0.3 V to VCC+ 0.3 V Input current at any pin 3/ 25 mA Package input current 3/ 50 mA Storage temperature range (TSTG) . -65C to +150C Power dissipation (PD) 4/ 875 mW Lead temperature (soldering, 10 seconds) . +300C Junction temperature (TJ) . +150C Thermal resistance, junction-to-

13、case (JC) . 7.5C/W Thermal resistance, junction-to-ambient (JA) 48C/W 1.4 Recommended operating conditions. Supply voltage range (DVCC= AVCC) . +4.5 V to +5.5 V Ambient operating temperature range (TA) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The

14、following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufactur

15、ing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Micro

16、circuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this dr

17、awing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Ext

18、ended operation at the maximum levels may degrade performance and affect reliability. 2/ All voltages are measured with respect to GND (GND = AGND = DGND), unless otherwise specified. 3/ When the input voltage (VIN) at any pin exceeds the power supply rails (VINVCC) the absolute value of current at

19、that pin should be limited to 25 mA or less. The 50 mA package input current limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to two. 4/ The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax, JAand the ambien

20、t temperature TA. The maximum allowable power dissipation at any temperature is PD= (TJmax TA)/JAor the number given in the absolute maximum ratings, whichever is lower. In most cases the maximum derated power dissipation will be reached only during fault conditions. Provided by IHSNot for ResaleNo

21、reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95593 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device

22、 classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device cla

23、ss M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or M

24、IL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.3 Electrical performance characteristics and postirradiation p

25、arameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall

26、be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasib

27、le due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in acc

28、ordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of comp

29、liance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be liste

30、d as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535

31、and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of micro

32、circuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device

33、 class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for devic

34、e class M. Device class M devices covered by this drawing shall be in microcircuit group number 81 (see MIL-PRF-38535, appendix A).Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95593 DEFENSE SUPPLY CENTER C

35、OLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA+125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max CONVERTER CHACTERISTICS Resolution RES 1, 2, 3 01 12 B

36、its Differential linearity error DLE 1 01 -0.8 +0.8 LSB 2, 3 -0.95 +0.95 Integral linearity error ILE 2/ 1 01 -1.0 +1.0 LSB 2, 3 -1.5 +1.5 Offset error OE 1 01 -1.25 +1.25 LSB 2, 3 -2.0 +2.0 Full scale error FSE 1 01 -1.0 +1.0 LSB 2, 3 -1.5 +1.5 Power supply sensitivity PSRR DVCC= AVCC= 5 V 10% 1, 2

37、, 3 01 -1.0 +1.0 LSB Reference resistance RREF1, 2, 3 01 500 1000 VREF+ (sense) input voltage VREF+ 1, 2, 3 01 AVCCV VREF- (sense) input voltage VREF- 1, 2, 3 01 AGND V Input voltage range VINTo VIN1, VIN2, or ADC IN 1, 2, 3 01 AGND 0.05 V AVCC+ 0.05 V V ADC IN input leakage IINLAGND to AVCC 0.3 V 1

38、, 2, 3 01 3 A MUX on-channel leakage IONLAGND to AVCC 0.3 V 1, 2, 3 01 3 A MUX off-channel leakage IOFFLAGND to AVCC 0.3 V 1, 2, 3 01 3 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZ

39、E A 5962-95593 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics continued. Test Symbol Conditions 1/ -55C TA+125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max DYNAMI

40、C CHACTERISTICS 3/ Signal-to-noise plus distortion ratio SINAD 4/ 4, 5, 6 01 68.0 dB Signal-to-noise ratio SNR 4/, 5/ 4, 5, 6 01 69.5 dB Total harmonic distortion THD 4/, 6/ 4 01 -74 dBc 5, 6 -70 Effective number of bits ENOB 4/, 7/ 4, 5, 6 01 11 Bits DC CHARACTERISTICS Logical 1 input voltage VIN1D

41、VCC= AVCC= +5.5 V 1, 2, 3 01 2.0 V Logical 0 input voltage VIN0DVCC= AVCC= +4.5 V 1, 2, 3 01 0.8 V Logical 1 input current IIN11, 2, 3 01 1.0 A Logical 0 input current IIN01, 2, 3 01 1.0 A Logical 1 output voltage VOUT1DVCC= AVCC= +4.5 V, IOUT= -360 A 1, 2, 3 01 2.4 V DVCC= AVCC= +4.5 V, IOUT= -100

42、A 4.25 Logical 0 output voltage VOUT0DVCC= AVCC= +4.5 V, IOUT= 1.6 mA 1, 2, 3 01 0.4 V TRI-STATE 0 output leakage current IOUTPins DB0-DB11 1, 2, 3 01 3 A DVCCsupply current DICC1, 2, 3 01 3 mA AVCCsupply current AICC1, 2, 3 01 12 mA See footnotes at end of table. Provided by IHSNot for ResaleNo rep

43、roduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95593 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics continued. Test Symbol Conditions 1/

44、-55C TA+125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max AC CHACTERISTICS Maximum sampling rate (1/tTHROUGHPUT) fS9, 10, 11 01 1 MHz Conversion time ( HS/ low to EOC high) tCONV9, 10, 11 01 600 980 ns HS/ pulse width t HS/ 9, 10, 11 01 5 550 ns HS/ low to EOC low tEO

45、C9, 10, 11 01 60 125 ns Access time ( RD low or OE high to data valid) tACCCL= 100 pF 9, 10, 11 01 20 ns TRI-STATE control ( RD high or OE low databus TRI-STATE) t1ht0hRL= 1 k, CL= 10 pF 9, 10, 11 01 40 ns Delay from RD low to INT high t HINT CL= 100 pF 9, 10, 11 01 60 ns Delay from EOC high to INT

46、low t LINT CL= 100 pF 9, 10, 11 01 -10 ns EOC high to new data valid tUPDATE9, 10, 11 01 15 ns Multiplexer address setup time (MUX address valid to EOC low) tMS9, 10, 11 01 50 ns Multiplexer address hold time (EOC low to MUX address invalid) tMH9, 10, 11 01 50 ns CS setup time ( CS low to RD low, HS

47、/ low, or OE high) t SCS 9, 10, 11 01 20 ns CS hold time ( CS high after RD high, HS/ high, or OE low) t HCS 9, 10, 11 01 20 ns 1/ DVCC= AVCC= +5 V, VREF+ (sense) = +4.096 V, VREF- (sense) = AGND, and fS= 1 MHz. 2/ Integral linearity error is the maximum deviation from a straight line between the me

48、asured offset and full scale endpoints. 3/ DVCC= AVCC= +5 V, VREF+ (sense) = +4.096 V, VREF- (sense) = AGND, and fS= 1 MHz, RS= 25, fIN= 100 kHz, 0 dB from fullscale. 4/ Dynamic testing of the device is performed using the ADC IN input. The input multiplexer adds harmonic distortion at high frequencies. 5/ The signal-to-noise ratio is the ratio of the signal amplitude to the background noise level. Harmonics of the input signal are not included in its calculation. 6/ The contributions from