DLA SMD-5962-95621 REV D-2010 MICROCIRCUIT DIGITAL RADIATION HARDENED CMOS PRESETTABLE UP DOWN COUNTER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R164-97. 97-02-24 Monica L. Poelking B Changes in accordance with NOR 5962-R377-97. 97-07-24 Raymond Monnin C Incorporate revisions A and B. Update boilerplate to MIL-PRF-38535 requirements. Editorial changes t

2、hroughout. LTG 03-09-12 Thomas M. Hess D Update radiation features in section 1.5 and paragraphs 4.4.4.1 4.4.4.5. Update boilerplate paragraphs to the current MIL-PRF-38535 requirements. - LTG 10-04-19 Thomas M. Hess REV SHET REV D D D D D D D D D SHEET 15 16 17 18 19 20 21 22 23 REV STATUS REV D D

3、D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Joseph A. Kerby DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTM

4、ENT OF DEFENSE CHECKED BY Monica L. Poelking APPROVED BY Monica L. Poelking MICROCIRCUIT, DIGITAL, RADIATION HARDENED CMOS, PRESETTABLE UP/DOWN COUNTER, MONOLITHIC SILICON DRAWING APPROVAL DATE 96-01-29 AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-95621 SHEET 1 OF 23 DSCC FORM 2233 APR 97 5

5、962-E216-10 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95621 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing docum

6、ents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness

7、Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 R 95621 01 V X C Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Leadfinish (see 1.2.5) / (see 1.2.3) / Drawing

8、 number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA de

9、signator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 4029B Radiation hardened CMOS, presettable up/down counter 02 4029BN Radiation hardened CMOS, presettable up/down counter

10、 with neutron irradiation die 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class leve

11、l B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E CDIP2-T16 16 Dual-in-lin

12、e X CDFP4-F16 16 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING S

13、IZE A 5962-95621 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VDD) . -0.5 V dc to +20 V dc Input voltage range -0.5 V dc to VDD+ 0.5 V dc DC input current, any one input 10 mA Devi

14、ce dissipation per output transistor 100 mW Storage temperature range (TSTG) -65C to +150C Lead temperature (soldering, 10 seconds) . +265C Thermal resistance, junction-to-case (JC): Case E . 24C/W Case X . 29C/W Thermal resistance, junction-to-ambient (JA): Case E . 73C/W Case X . 114C/W Junction t

15、emperature (TJ) . +175C Maximum power dissipation at TA= +125C (PD): 4/ Case E . 0.68 W Case X . 0.44 W 1.4 Recommended operating conditions. Supply voltage range (VDD) . 3.0 V dc to +18 V dc Case operating temperature range (TC) -55C to +125C Input voltage (VIN) . 0 V to VDDOutput voltage (VOUT) .

16、0 V to VDD1.5 Radiation features. Maximum total dose available (dose rate = 50 - 300 rads (Si)/s) 1 x 105rads (Si) Single event phenomenon (SEP): effective linear energy threshold, no upsets (see 4.4.4.5) 75 MeV/(cm2/mg) 5/ effective LET no latchup (see 4.4.4.5) 75 MeV/(cm2/mg) 5/ Dose rate upset (2

17、0 ns pulse) . 5 x 108 rads(Si)/s 5/ Dose rate latch-up . 2 x 108rads(Si)/s 5/ Dose rate survivability . 5 x 1011rads(Si)/s 5/ Neutron irradiated (for device type 02) . 1 x 1014neutrons/cm21/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at th

18、e maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to VSS. 3/ The limits for the parameters specified herein shall apply over the full specified VDDrange and case temperature range of -55C to +125C unless otherwise noted. 4/ If

19、 device power exceeds package dissipation capability, provide heat sinking or derate linearly (the derating is based on JA) at the following rate: Case E . 13.7 mW/C Case X . 8.8 mW/C 5/ Guaranteed by design or process but not tested. Provided by IHSNot for ResaleNo reproduction or networking permit

20、ted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95621 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standa

21、rds, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.

22、 DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of th

23、ese documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited

24、herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance wi

25、th MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-3

26、8535, appendix A for non-JAN class level B devices and as specified herein. 3.1.1 Microcircuit die. For the requirements for microcircuit die, see appendix A to this document. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified i

27、n MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table

28、. The truth table shall be as specified on figure 2. 3.2.4 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical perform

29、ance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. Provided by IHSNot for ResaleNo r

30、eproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95621 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 3.4 Electrical test requirements. The electrical test requirements shall be the sub

31、groups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due t

32、o space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance

33、with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance.

34、For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an

35、approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and here

36、in or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits

37、 delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M

38、. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class

39、M. Device class M devices covered by this drawing shall be in microcircuit group number 40 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95621 DEFENSE SUPPLY CENTER COLUMBUS

40、 COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. Test Symbol Test conditions -55C TC +125C unless otherwise specified Devicetype Group A subgroups Limits Units Min Max Supply current IDDVDD= 5 V VIN= 0.0 V or VDDAll 1, 3 1/ 5

41、.0 A 2 1/ 150 VDD= 10 V VIN= 0.0 V or VDDAll 1, 3 1/ 10 2 1/ 300 VDD= 15 V VIN= 0.0 V or VDDAll 1, 3 1/ 10 2 1/ 600 VDD= 20 V, VIN= 0.0 V or VDDAll 1 10 2 1000 M, D, P, L, R 2/ All 1 25 VDD= 18 V, VIN= 0.0 V or VDDAll 3 10 Low level output current (sink) IOLVDD= 5 V VO= 0.4 V VIN= 0.0 V or VDDAll 1

42、0.53 mA 2 1/ 0.36 3 1/ 0.64 VDD= 10 V VO= 0.5 V VIN= 0.0 V or VDDAll 1 1.4 2 1/ 0.9 3 1/ 1.6 VDD= 15 V VO= 1.5 V VIN= 0.0 V or VDDAll 1 3.5 2 1/ 2.4 3 1/ 4.2 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICR

43、OCIRCUIT DRAWING SIZE A 5962-95621 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics Continued. Test Symbol Test conditions -55C TC +125C unless otherwise specified Device type Group A subgroups Li

44、mits Units Min Max High level output current (source) IOHVDD= 5 V VO= 4.6 V VIN= 0.0 V or VDDAll 1 -0.53 mA 2 1/ -0.36 3 1/ -0.64 VDD= 5 V VO= 2.5 V VIN= 0.0 V or VDDAll 1 -1.8 2 1/ -1.15 3 1/ -2.0 VDD= 10 V VO= 9.5 V VIN= 0.0 V or VDDAll 1 -1.4 2 1/ -0.9 3 1/ -2.6 VDD= 15 V VO= 13.5 V VIN= 0.0 V or

45、 VDDAll 1 -3.5 2 1/ -2.4 3 1/ -4.2 Output voltage, high VOHVDD= 5 V, no load 1/ All 1, 2, 3 4.95 V VDD= 10 V, no load 1/ 1, 2, 3 9.95 VDD= 15 V, no load 3/ 1, 2, 3 14.95 Output voltage, low VOLVDD= 5 V, no load 1/ All 1, 2, 3 0.05 V VDD= 10 V, no load 1/ 1, 2, 3 0.05 VDD= 15 V, no load 1, 2, 3 0.05

46、Input voltage, low 4/ VILVDD= 5 V VOH 4.5 V, VOL9.0 V, VOL13.5 V, VOL4.5 V, VOL9.0 V, VOL13.5 V, VOLVDD/2 VOL1F between VDDand VSS. 8/ From CARRY IN to clock edge. TABLE IB. SEP test limits. 1/ 2/ 7/ Device type VDD= 3.0 V 3/ Bias for latch-up test VDD= 3.6 V no latch-up LET = 4/ 5/ MeV/(mg/cm2) Eff

47、ective LET no upsets MeV/(mg/cm2) All LET 75 6/ 75 1/ For SEP test conditions, see 4.4.4.5 herein. 2/ Technology characterization and model verification supplemented by in-line data may be used in lieu of end-of-line testing. Test plan must be approved by TRB and qualifying activity. 3/ Tested for u

48、psets at worst case temperature, TA= +25C 10C. 4/ Tested at worst case temperature, = +125C 10C for latch-up. 5/ Tested to a LET of 75 MeV/(mg/cm2), with no latch-up (SEL). 6/ Tested to a LET of 75 MeV/(mg/cm2) with no single event upsets (SEU). 7/ Guaranteed by design or process but not tested. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95621 DEFENSE SUPPLY CENTER COLUMBUS