DLA SMD-5962-95762-1995 MICROCIRCUIT DIGITAL FAST CMOS BUFFER CLOCK DRIVER WITH INVERTING THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS AND LIMITED OUTPUT VOLTAGE SWING MONOLITHIC SILI.pdf

1、SMD-5962-95762 = 9999996 0083490. bb3 E LTR t DATE (YR-MO-DA) APPROVED DESCRIPTION REVI SI ONS MICROCIRCUIT, DIGITAL, FAST CMOS, BUFFERELOCK DRIVER WITH INVERTING INPUTS AND LIMITED OUTPUT VOLTAGE SWING, THREE-STATE OUTPUTS, TTL COMPATIBLE 1 MONOLITHIC SILICON REV SHEET REV REV STATUS OF SHEETS PMIC

2、 NIA STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS PREPARED BY Thanh V. Nguyen CHECKED BY Thanh V. Nguyen APPROVED BY Monica L. Poelking AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 95-1 1-08 I I REVISION LEVEL AMSC NIA DEFENSE ELECTRONICS SUPP

3、LY CENTER DAYTON, OHIO 45444 SIZE CAGE CODE A I67268 I 5962-95762 SHEET 1 OF 19 DESC FORM 193 JUL 94 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. 5962-El 26-96 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5

4、9b2-95762 m 9999996 008L49L 5TT m 1. SCOPE 1.1 a. This drawing forms a part of a one part - one part nunber docmentation system (see 6.6 herein). Two woduct assurance classes consisting of military high reliability (device classes P and M) and space application device class V), and a choice of case

5、outlines and lead finishes are available and are reflected in the Part or Identifying NB= 2.0 V For all other inputs Three-state output leakage current 1 ow 3020 VOUT = GND VIN = Vcc or GND pA pA Input current high 301 O For input wider test, VIN = Vcc For all other inputs, VIN = V or GES _ Input cu

6、rrent low 3009 For input under test, VIN = GND For all other inputs, VIN = Vc or GNS pA Output short circuit current 301 1 m4 For all inputs, VIN = Vcc or GND VwT GND pA Input/output power off leakage current 301 1 For input or output under test VIN or VwT = 4.5 V All other pins at 0.0 V Dynamic pou

7、er supply current Puiescent supply current delta, TTL input Level 3005 Outputs open For input under test For all other inputs VIN = Vcc or GND VIN = 3.4 v nd Puiescent supply current, outputs high 3005 Al 1 - Al 1 - OEA = OEB = GND For all other inputs VIN = Vcc or GND Puiescent supply current, outp

8、uts 1 ow 3005 1, 2, 3 rrd See footnotes at end of table. t I 5962-95762 STAN DARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I SHEET REVISION LEVEL DESC FORM 19% JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SI

9、ZE A STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL 5962-95762 SHEET 7 TABLE I. Electrical wrformance characteristics - Continued. Test and test method I/ MI L -STD-883 Test conditions u -55C a TC a +125“C unless otherwise specified +4.5 v a va 5 +5

10、.5 v - Max 0.5 - - 3.0 - 4.0 - 55.5 - 57.5 - 6.0 - 8.0 Quiescent supply current, outputs disabled 3005 - OEA = OEB = Vcc For all other inputs VIN = Vcc or GND Qgtputsppen - OE = OEg = GNO MO output toggling f = 25 MHz 58% duty cycle For nonswitching For Switching inwts Total supply current For switc

11、hing inputs VIN = 3.4 v or GND input, VIN = Vcc or GND Qgtputsopen OEA = OEB = GND Eleven outputs toggling f = 50 MHz 58% duty cycle For nonswi tching Al 1 - Al 1 - Al 1 - Al 1 - Al 1 - Al 1 For sui tching inputs V For switching inputs VIN 3.4 V or GND input, VIN = Vcs or GN TC = +25“C See 4.4.lb In

12、put capacitance Output capacitance 3012 3012 Low level ground bounce noise V TF= f.25C See figure 4 = 3.0 V, VIL = 0.0 V High level Vcc bounce noise w VIH = 2.0 V, VIL = 0.8 V Verify output Vo See 4.4.1 Func t i ona 1 test 3014 Propagation delay - time, INA to- OAn, IN JO OBn, IN to iON 3013 Propaga

13、tion delay time, oumt =able OEA and the absolute value of the magnitude, not the sign, is relative to the minim and maximm limits, as applicable, listed herein. All devices shall meet or exceed the limits specified in table I at 4.5 V s Vcc i 5.5 V. 4/ This parameter is guaranteed, if not tested, to

14、 the limits specified in table I herein. Output terminals not designated shall be high level logic, low level logic, or op, 2 r/ Three-state output conditions are required. / 6/ This test may be performed using VIH = 3.0 V. z/ Not more than one output should be tested at a time. lhe duration of the

15、test should not exceed one second. 8/ Ica may be verified by the following equation: hen VIH = 3.0 V is used, the test is guaranteed for VIH = 2.0 V. ICCT Icc DHNTAICC fcp/2 + folo ICCD = where IC,-, IcC (Icck or ICCH in table I), and AIc shall be the measured values of these parameters, for the dev

16、ice under test, w en tested as described in tabFe I, herein. lhe values for DH, NT, fCp, fo, and No shall be as listed in the test conditions colum for ICCT e/ This test may be performed either one input at a time (preferred method) or with all input pins simultaneously at VIN = v - 2.1 V (alternate

17、 method). using tkg alternate test method, the maximm limit is equal to the nunber of inputs at a high TTL input level times 2.0 mA; and the preferred method and limits are guaranteed. in table 1, herein. Classes P and V shalt use the preferred method. When the test is performed STAN DARD MICROCIRCU

18、IT DRAWING DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO 45444 I 5962-95762 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-75762 m 9999996 0081498 954 m SIZE A STANDARD MICROCIRCUIT DRAWING DEFENSEELECTRONICSSUPPLYCENTER

19、 DAYTON, OHIO 45444 REVISION LEVEL TABLE I. Electrical rx rformance characteristics - Continued. 5962-95762 SHEET 9 o/ ICCT is calculated as follows: where I Dr=-Duty cycle for TTL inputs at 3.4 V N - Number of TTL inputs at 3.4 V Alc. = Quiescent supply current delta, TTL inputs at 3.4 V I fCCD=-Cl

20、ock frequency for registered devices (fCp = O for nonregistered devices) f:= Output frequency No = Nunber of outputs at fo - Quiescent supply current (any IccL or IccH) - Dynamic pouer supply current caused by an input transition pair (HLH or LHL) u This test is required only for group A testing; se

21、e 4.4.1 herein. -?/ This test is for qualification only. Ground and V bounce tests are performed on a non-switching (quiescent) output and are used to measure the magnitude of iduced noise caused by other simultaneously switching outputs. The test is performed on a low noise bench test fixture. with

22、 500 of load resistance and a minim of 50 PF of load capacitance (see figure 4). resistors shall be used. It is suggested, that whenever possible, this distance be kept to less than 0.25 inches. shall be placed in parallel from Vcc to ground. the device manufacturer. a 1 GHz minim banduidth oscillos

23、cope with a 50n input impedance. The device inputs shall be conditioned such that all outputs are at a high naninal VoH level. The device inputs shall then be conditioned such that they switch simultaneously and the output under test remains at V other outputs possible are switched from VOH to VOL:

24、VoHy and VOHP are then measured from the nomina?HVOH level to the largest negative and positive peaks, respectively see figure 4). outputs not under test switching from VOL to VOH. The device inputs shall be conditioned such that all outputs are at a low nominal VOL level. shall then be conditioned

25、such that they switch simultaneously and the output under test remains at V other outputs possible are switched from VOL to VOH. VoLp and VoLv are then measured from the nomina? VOL level to the largest positive and negative peaks, respectively (see figure 4). outputs not under test switching from V

26、OH to VOL. The V shallc OUTPUT n NOTES: 1. C tke test jig and probe. 2. RL = 4500 11 percent, chip resistor in series with a 50 termination. termination shall be the 50 characteristic impedance of the coaxial connector to the oscilloscope. 3. Input signal to the device under test: a. b. includes a 4

27、7 pF chip capacitor (-0 percent, +20 percent) and at least 3 pF of equivalent capacitance frcm For monitored outputs, the 50Q VIN 0.0 V to 3.0 V; duty cycle 50 percent; fIN 2-1 MHz. tr, tf =-3 ns 11.0 ns. 3.0 ns limit may be increased up to 10 ns, as needed, maintaining the 21.0 ns tolerance and gua

28、ranteeing the results at 3.0 ns 11.0 ns; skew between any two switching inputs signals (tsk): For input signal generators incapable of maintaining these values of tr and tf, the s 250 ps. FIGURE 4. Ground bounce load c i rcui t and wavefo rm. STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95762 I Provide

29、d by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-2.7 v 1.5 v 0.3 v 0.0 v PLH t I INPUT Ir“ - - - tPZL OUTPUT OUTPUT - PLZ NVCC 1.5 V VOL + 0.3 V I VOL dtf k n MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL SHEET 13 O

30、UTPUT VOH VOH - 0.3 V 1.5 V s GNO FIGURE 5. Suitchina waveforms and test circuit. STANDARD I Y I I 5962-95762 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-95762 ib 0083503 043 = INPUT 2 ti - OUTPUT 1 OUTPUT 2 3.0 1.5

31、 ti - - J OH 1.5 VOL h= -rL tSK i01 OH - t 3.0 INPUT 1.5 0.0 OH OUTPUT 1.5 tSKP FIGURE 5. Switchina uaveforms and test c ircuit - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I 5962-95762 _ _ 1 REVISION LEVEL I I I DESC FORM 193A JUL 94 Provided by IH

32、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-INPUT SIZE STANDARD A MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL 3.0 V 1.5 v 5962-95762 SHEET 15 OH PACKAGE 1 OUTPUT 1.5 V -I VOL - tSKtl %KtI “OH PACKAGE 2 OUTPUT 1.5 v

33、- tPHL2 - tPLH2 vcc P OTHER INPUTS TIED TO VCC OR GND 1 v P AS REQUIRED PULSE GENERATOR -I- - NOTES: 1. When measuring tpLZ and tpZL: VTEST = 7.0 V. 2. when measuring tpHZ, tpZH, tpLH, and tpH : 3. The tp is at 6oL except when disabled by the output enable control. The tpZH and tpHZ reference uavefo

34、rm is for the output under test with internal conditions such that the output is at VOH except when disabled by the output enable control. CL = 50 pF minimum or equivalent (includes test jig and probe capacitance). RL = 500n or equivalent. RT = 5On or equivalent. Input signal from pulse generator: V

35、IN = 0.0 V to 3.0 V; PRR s 10 MHz; t shall be measured from 0.3 V to 2.7 V and from 2.7 V to 0.3 V, respectivery; duty cycle = 50 percent. Timing parameters shall be tested at a minim input frequency of 1 MHz. The outputs are measured one at a time with one transition per measurement. VTEST = open.

36、and tpLZ reference waveform is kor the output under test with internal conditions such that the output 4. 5. 6. 7. 8. 9. s 2.5 ns; tf s 2.5 ns; tr and tf FIGURE 5. Suitchino waveforms and test circuit - Continued. DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permi

37、tted without license from IHS-,-,-STAN DARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 DESC FORM 193A JUL 94 SIZE A 5962-95762 REVISION LEVEL SHEET 16 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TABLE II. Elect rica

38、 1 test reauirements. Final electrical parameters (see 4.2) Group A test Group C end-point electrical Group D end-point electrical Group E end-point electrical requirements (see 4.4) parameters (see 4.4) parameters (see 4.4) parameters (see 4.4) Test requirements 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 58 6,

39、7, 8, 9, IO, 11 7, 8, 9, IO, 11 1/ 1/ 1, 2, 3, 4, 5, 6, 7, 8, 9, IO, 11 7, 8, 9, 10, 11 1, 2, 3, 4, 5, 6 1, 2, 3 1, 4, 7. 9 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6 1, 2, 3 1. 4, 7, 9 Interim electrical parameters (see 4.2) SIZE A STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHI

40、O 45444 REVISION LEVEL Subgroups Subgroups (in accordance uith MIL-STD-883, (in accordance with MIL- 1-38535, table I I I) Device Device Device class P class V class M 5962-95762 SHEET 17 1 1 1, 2, 3, 4, 5, 6, 7, 8, 9, IO, 11 2/ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 1, 2, 3. 4, 5, 6 7, 8, 9, 10, 1 1, 2,

41、 3 I 1, 4, 7, 9 1/ PDA applies to subgroups 1 and 4 (i.e., lCcT only). 1/ PDA applies to subgroups 1, 4, and 7. 4.4.2.1 Additional criteria for device class M. Steady-state life test conditions, method 1005 of MIL-STO-883: a. Test condition A, 6, C or D. level control and shall be made available to

42、the preparing or acquiring activity upon request. circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005. The test circuit shall be maintained by the manufacturer under docwnt revision The test b. TA = +125

43、*C, minim. c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STO-883. 4.4.2.2 Additional criteria for device classes Q and v. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturers GI

44、M plan in accordance dith MIL-1-38535. The test circuit shall be maintained under docunent revision levellcontrol of the device nanufacturers TRB in accordance uith MIL-1-38535 and shall be made available to the preparing or acquiring activity ipon request. The test circuit shall specify the inputs,

45、 outputs, biases, and puer dissipation, as applicable, in xcordance with the intent specified in test method 1005. 4.4.3 CrouD D inswct ion. The group D inspection end-point electrical parameters shall be as specified in table II rerein. 4.4.4 GrOUD E inswction. Group E inspection is required only f

46、or parts intended to be marked as radiation iardness assured (see 3.5 herein). jevice class M shall be M and D. RHA levels for device classes P and V shall be M, D, L, R, F, G, and H and for a. b. End-point electrical parameters shall be as specified in table II herein. For device class M, the devic

47、es shall be subjected to radiation hardness assured tests as specified in MIL-1-38535, appendix A, for the RHA level being tested. vehicle shall be subjected to radiation hardness assured tests as specified in MIL-1-38535 for the RHA level being tested. All device classes must meet the postirradiati

48、on end-point electrical parameter limits as defined in table I at TA = +25C -+5C, after exposure, to the subgroup specified in table II herein. c. When specified in the purchase order or contract, a copy of the RHA delta limits shall be supplied. For device classes P and V, the devices or test DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- - SMD-5962-75762 9999996 0081507 797 rn 4.5 nethods of insoect ion. Methods of inspection shall be specified as follows: 4.5.1 yoltase and CU rrent. Unless otherwise specified,