DLA SMD-5962-96543 REV G-2012 MICROCIRCUIT DIGITAL ADVANCED CMOS RADIATION HARDENED QUADRUPLE 2-INPUT NAND SCHMITT TRIGGER TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R121-97. - TVN 96-12-12 Monica L. Poelking B Changes in accordance with NOR 5962-R258-97. - CFS 97-04-22 Monica L. Poelking C Changes in accordance with NOR 5962-R080-99. - JAK 99-09-10 Monica L. Poelking D Add

2、 limit for linear energy threshold (LET) with no latch-up in section 1.5. Update the boilerplate to the requirements of MIL-PRF-38535. Editorial changes throughout. - TVN 05-10-21 Thomas M. Hess E Add appendix A, microcircuit die. - TVN 06-02-07 Thomas M. Hess F Correct the title. Add equivalent tes

3、t circuit in figure 1. Update die appendix. Update the boilerplate to the requirements of MIL-PRF-38535. Editorial changes throughout. - jak 12-04-10 Thomas M. Hess G To correct switching waveforms input/output test limits to figure 4. Add test equivalent circuits and footnote 4 to figure 4. Delete

4、class M requirements throughout.- MAA 12-12-10 Thomas M. Hess REV SHEET REV G G G G G G G G G SHEET 15 16 17 18 19 20 21 22 23 REV STATUS OF SHEETS REV G G G G G G G G G G G G G G SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Thanh V. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3

5、990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Thanh V. Nguyen APPROVED BY Monica L. Poelking MICROCIRCUIT, DIGITAL, ADVANCED CMOS, RADIATION HARDENED,QUADRUPLE 2-I

6、NPUT NAND SCHMITT TRIGGER, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 96-05-31 REVISION LEVEL G SIZE A CAGE CODE 67268 5962-96543 SHEET 1 OF 23 DSCC FORM 2233 APR 97 5962-E081-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-ST

7、ANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-96543 REVISION LEVEL G SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device cla

8、ss V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 G 96543 01 V X A Fede

9、ral RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are ma

10、rked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54ACTS132 Radiation hardened, quadruple 2-input NAND Schmitt trigger, TTL compatible inpu

11、ts 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in

12、MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style C GDIP1-T14 or CDIP2-T14 14 Dual-in-line X CDFP3-F14 14 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. Provided by IHSNot for ResaleNo reproduction or

13、 networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-96543 REVISION LEVEL G SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VDD) -0.3 V dc to +7.0 V dc DC input voltage

14、range (VIN) -0.3 V dc to VDD + 0.3 V dc DC output voltage range (VOUT) . -0.3 V dc to VDD+ 0.3 V dc DC input current, any one input (IIN). 10 mA Latch-up immunity current (ILU) 150 mA Storage temperature range (TSTG) . -65C to +150C Lead temperature (soldering, 5 seconds) +300C Thermal resistance, j

15、unction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C Maximum power dissipation (PD) . 1.0 W 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (VDD) +4.5 V dc to +5.5 V dc Input voltage range (VIN) 0.0 V dc to VDDOutput voltage range (VOUT). 0.0 V dc to VDDMaximum in

16、put rise or fall time at VDD= 4.5 V (tr, tf) 1 ns/V 4/ Case operating temperature range (TC) . -55C to +125C 1.5 Radiation features. 5/ Maximum total dose available (dose rate = 50 300 rads (Si)/s) 5 x 105Rads (Si) Single event phenomenon (SEP): No SEU occurs at effective LET (see 4.4.4.4) . 80 MeV-

17、cm2/mg 6/ No SEL occurs at effective LET (see 4.4.4.4) . 120 MeV-cm2/mg 6/ Dose rate upset (20 ns pulse) 1 x 109Rads (Si)/s 6/ Latch-up . None 6/ Dose rate survivability 1 x 1012Rads (Si)/s 6/ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation

18、at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise specified, all voltages are referenced to VSS. 3/ The limits for the parameters specified herein shall apply over the full specified VDDrange and case temperature range of -55C to +125C unless otherwise specifi

19、ed. 4/ Derate system propagation delays by difference in rise time to switch point for tror tf 1 ns/V. 5/ Radiation testing is performed on the standard evaluation circuit (SEC). 6/ Limits are guaranteed by design or process, but not production tested unless specified by the customer through the pur

20、chase order or contract. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-96543 REVISION LEVEL G SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Govern

21、ment specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATI

22、ON MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Mi

23、crocircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. T

24、he following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. ASTM INTERNATIONAL (ASTM) ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) I

25、nduced by Heavy Ion Irradiation of semiconductor Devices. (Copies of these documents are available online at http:/www.astm.org/ or from ASTM International, 100 Barr Harbor Drive, P.O. Box C700, West Conshohocken, PA, 19428-2959). JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD 20 - Standard f

26、or Description of 54/74ACXXXX and 54/74ACTXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org/ or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2701.) 2.3 Order of precedence. In the ev

27、ent of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. Provided by IHSNot for ResaleNo reproduction or

28、networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-96543 REVISION LEVEL G SHEET 5 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be

29、 in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.1.1 Microcircuit die. For the requirements of microcircuit die, see ap

30、pendix A to this document. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Termina

31、l connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuit. The switching waveforms and test circ

32、uit shall be as specified on figure 4. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and post irradiation parameter limits are as specified in table IA and shall apply over the full case

33、operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the man

34、ufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for devi

35、ce classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be r

36、equired from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product m

37、eets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for Resa

38、leNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-96543 REVISION LEVEL G SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. Test Symbol Test conditions 1/ -55C

39、TC +125C unless otherwise specified Device type VDDGroup A subgroups Limits 2/ Unit Min Max Schmitt trigger positive-going threshold VT+ All 4.5 V 1, 2, 3 2.25 V M, D, P, L, R, F, G 3/ All 1 2.25 All 5.5 V 1, 2, 3 2.25 M, D, P, L, R, F, G 3/ All 1 2.25 Schmitt trigger negative-going threshold VT- Al

40、l 4.5 V 1, 2, 3 0.5 V M, D, P, L, R, F, G 3/ All 1 0.5 All 5.5 V 1, 2, 3 0.5 M, D, P, L, R, F, G 3/ All 1 0.5 Hysteresis (VT+- VT-) VH All 4.5 V 1, 2, 3 0.3 0.9 V M, D, P, L, R, F, G 3/ All 1 0.3 0.9 High level output voltage VOH For all inputs affecting output under test, VIN= VDDor VSSIOH= -8 mA A

41、ll 4.5 V 1, 2, 3 3.15 V M, D, P, L, R, F, G 3/ All 1 3.15 Low level output voltage VOL For all inputs affecting output under test, VIN= VDDor VSSIOL= 8 mA All 4.5 V 1, 2, 3 0.4 V M, D, P, L, R, F, G 3/ All 1 0.4 Input current high IIH For input under test, VIN= VDDFor all other inputs, VIN= VDDor VS

42、SAll 5.5 V 1, 2, 3 +1.0 A M, D, P, L, R, F, G 3/ All 1 +1.0 Input current low IIL For input under test, VIN= VSSFor all other inputs, VIN= VDDor VSSAll 5.5 V 1, 2, 3 -1.0 A M, D, P, L, R, F, G 3/ All 1 -1.0 Output current (source) IOH4/ For output under test, VOUT= VDD - 0.4 V VIN= VDDor VSSAll 4.5

43、V and 5.5 V 1, 2, 3 -8.0 mA M, D, P, L, R, F, G 3/ All 1 -8.0 Output current (sink) IOL4/ For output under test, VOUT= 0.4 V VIN= VDDor VSSAll 4.5 V and 5.5 V 1, 2, 3 8.0 mA M, D, P, L, R, F, G 3/ All 1 8.0 Quiescent supply current IDDQVIN= VDDor VSSAll 5.5 V 1, 2, 3 10.0 A M, D, P, L, R, F, G 3/ Al

44、l 1 10.0 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-96543 REVISION LEVEL G SHEET 7 DSCC FORM 2234 APR 97 TABLE IA. Electrica

45、l performance characteristics Continued. Test Symbol Test conditions 1/ -55C TC +125C unless otherwise specified Device type VDDGroup A subgroups Limits 2/ Unit Min Max Quiescent supply current delta, TTL input levels IDDQ 5/ For input under test, VIN= VDD- 2.1 V For all other inputs, VIN= VDDor VSS

46、All 5.5 V 1, 2, 3 3.1 mA M, D, P, L, R, F, G 3/ All 1 3.1 Short circuit output current IOS6/ 7/ VOUT= VDDand VSSAll 5.5 V 1, 2, 3 200 mA Input capacitance CINf = 1 MHz See 4.4.1c All 0.0 V 4 15.0 pF Output capacitance COUTf = 1 MHz See 4.4.1c All 0.0 V 4 15.0 pF Switching power dissipation PSW8/ CL=

47、 50 pF, per switching output All 4.5 V and 5.5 V 4, 5, 6 1.9 mW/ MHz M, D, P, L, R, F, G 3/ All 4 1.9 Functional test 9/ VIH= 2.25 V, VIL= 0.5 V See 4.4.1b All 4.5 V and 5.5 V 7, 8 L H M, D, P, L, R, F, G 3/ All 7 L H Propagation delay time, An or Bn to Yn tPLH10/ CL= 50 pF minimum See figure 4 All

48、4.5 V and 5.5 V 9, 10, 11 2.0 12.0 ns M, D, P, L, R, F, G 3/ All 9 2.0 12.0 tPHL10/ CL= 50 pF minimum See figure 4 All 4.5 V and 5.5 V 9, 10, 11 2.0 15.0 M, D, P, L, R, F, G 3/ All 9 2.0 15.0 1/ Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits, to the tests in table IA herein. Output terminals not designated shall be high level logic, low level logic, or open, except for the IDDQand IDDQtests, the output terminals shall be open. When performing the IDDQand IDDQtests, the current m