DLA SMD-5962-96559 REV D-2013 MICROCIRCUIT DIGITAL ADVANCED CMOS RADIATION HARDENED 8-BIT SERIAL PARALLEL-IN SERIAL-OUT SHIFT REGISTER TTL COMPATIBLE INPUTS MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R101-97 CFS. 96-11-18 Monica L. Poelking B Incorporate Revision A. Update boilerplate to MIL-PRF-38535 requirements. LTG 01-11-01 Thomas M. Hess C Correct title to more accurately describe the function. Update

2、radiation features in section 1.5. Update the boilerplate paragraphs to current requirements as specified in MIL-PRF-38535. - jak 10-01-19 Thomas M. Hess D To correct switching waveforms input/output test limits to figure 4. Add test equivalent circuits and footnote 4 to figure 4. Delete class M req

3、uirements throughout.MAA 13-01-25 Thomas M. Hess REV SHEET REV D D D D SHEET 15 16 17 18 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Thanh V. Nguyen DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil

4、STANDARD MICROCIRCUIT DRAWING CHECKED BY Thanh V. Nguyen THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A APPROVED BY Monica L. Poelking MICROCIRCUIT, DIGITAL, ADVANCED CMOS, RADIATION HARDENED, 8-BIT SERIAL/PARALLEL-IN, SERIAL-OUT SHIFT REGISTE

5、R, TTL COMPATIBLE INPUTS, MONOLITHIC SILICON DRAWING APPROVAL DATE 96-07-16 REVISION LEVEL D SIZE A CAGE CODE 67268 5962-96559 SHEET 1 OF 18 DSCC FORM 2233 APR 97 5962-E184-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAW

6、ING SIZE A 5962-96559 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case

7、outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 H 96559 01 V X C Federal RHA Device Device Ca

8、se Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriat

9、e RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54ACTS165 Radiation hardened, 8-bit serial/parallel-in, serial-out shift register 1.2.3 Device class designator.

10、The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline l

11、etter Descriptive designator Terminals Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line X CDFP4-F16 16 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license

12、from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96559 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VDD) -0.3 V dc to +7.0 V dc DC input voltage range (VIN) -0.3 V dc to VDD+ 0.3 V dc

13、 DC output voltage range (VOUT) . -0.3 V dc to VDD+ 0.3 V dc DC input current, any one input (IIN). 10 mA Latch-up immunity current (ILU) 150 mA Storage temperature range (TSTG) . -65C to +150C Lead temperature (soldering, 5 seconds) +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835

14、 Junction temperature (TJ) +175C Maximum package power dissipation (PD) . 1.0 W 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (VDD) +4.5 V dc to +5.5 V dc Input voltage range (VIN) +0.0 V dc to VDDOutput voltage range (VOUT). +0.0 V dc to VDDCase operating temperature range (TC) .

15、 -55C to +125C Maximum input rise and fall rate at VDD= 4.5 V (tr, tf) 1 ns/V 4/ 1.5 Radiation features. 5/ Maximum total dose available (dose rate = 50 300 rads (Si)/s) 1 x 106Rads (Si) Single event phenomenon (SEP): No SEU occurs at effective LET (see 4.4.4.4) . 80 MeV/(mg/cm2) 6/ No SEL occurs at

16、 effective LET (see 4.4.4.4) 120 MeV/(mg/cm2) 6/ Dose rate upset (20 ns pulse) 1 x 109Rads (Si)/s 6/ Dose rate latch-up . None 6/ Dose rate survivability 1 x 1012Rads (Si)/s 6/ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum l

17、evels may degrade performance and affect reliability. 2/ Unless otherwise noted, all voltages are referenced to VSS. 3/ The limits for the parameters specified herein shall apply over the full specified VDDrange and case temperature range of -55C to +125C unless otherwise noted. 4/ Derate system pro

18、pagation delays by difference in rise time to switch point for tror tf 1 ns/V. 5/ Radiation testing is performed on the standard evaluation circuit (SEC). 6/ Limits are guaranteed by design or process, but not production tested unless specified by the customer through the purchase order or contract.

19、 .Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96559 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, sta

20、ndards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Inte

21、grated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MI

22、L-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s

23、) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. ASTM INTERNATIONAL (ASTM) ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irr

24、adiation of semiconductor Devices. (Copies of these documents are available online at http:/www.astm.org or from ASTM International, 100 Barr Harbor Drive, P.O. Box C700, West Conshohocken, PA, 19428-2959). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the

25、references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be

26、 in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construct

27、ion, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The t

28、ruth table shall be as specified on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuits. The switching waveforms and test circuits shall be as specified on figure 4. Provided by IHSNot for ResaleNo reproduction or networking

29、 permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96559 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under docume

30、nt revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter lim

31、its are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are described in table IA. 3.5 Marking. The part s

32、hall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using t

33、his option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of complian

34、ce. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of

35、supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of

36、 microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96559 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electri

37、cal performance characteristics. Test Symbol Test conditions 1/ 2/ -55C TC +125C unless otherwise specified Device type VDDGroup A subgroups Limits 3/ Unit Min Max High level input voltage VIHAll 4.5 V 1, 2, 3 2.25 V All 5.5 V 1, 2, 3 2.75 Low level input voltage VILAll 4.5 V 1, 2, 3 0.8 V All 5.5 V

38、 1, 2, 3 0.8 High level output voltage VOHFor all inputs affecting output under test, VIN= VDDor VSSIOH= -8.0 mA All 4.5 V 1, 2, 3 3.15 V Low level output voltage VOLFor all inputs affecting output under test, VIN= VDDor VSSIOL= 8.0 mA All 4.5 V 1, 2, 3 0.4 V Input current high IIHFor input under te

39、st, VIN= 5.5 V For all other inputs VIN= VDDor VSSAll 5.5 V 1, 2, 3 +1.0 A Input current low IILFor input under test, VIN= VSSFor all other inputs VIN= VDDor VSSAll 5.5 V 1, 2, 3 -1.0 A Output current (Sink) IOL 4/ VIN= VDDor VSSVOL= 0.4 V All 4.5 V and 5.5 V 1, 2, 3 8.0 mA Output current (Source) I

40、OH 4/ VIN= VDDor VSSVOH= VDD-0.4 V All 4.5 V and 5.5 V 1, 2, 3 -8.0 mA Quiescent supply current delta, TTL input levels IDD5/ For input under test VIN= VDD2.1 V For all other inputs VIN= VDDor VSSAll 5.5 V 1, 2, 3 1.6 mA See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or

41、networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96559 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics Continued. Test Symbol Test conditions 1/ 2/ -55C TC +125C

42、 unless otherwise specified Device type VDDGroup A subgroups Limits 3/ Unit Min Max Quiescent supply Current IDDQVIN= VDDor VSSAll 5.5 V 1, 2, 3 10.0 A Short circuit output current IOS6/ 7/ VOUT= VDDand VSSAll 5.5 V 1, 2, 3 200 mA Input capacitance CINf = 1 MHz, see 4.4.1c All 0.0 V 4 15.0 pF Output

43、 capacitance COUTf = 1 MHz, see 4.4.1c All 0.0 V 4 15.0 pF Switching power Dissipation PSW8/ CL= 50 pF, per switching output All 4.5 V and 5.5 V 4, 5, 6 2.9 mW/MHz Functional test 9/ VIH= 0.5 VDD, VIL= 0.8 V See 4.4.1b All 4.5 V and 5.5 V 7, 8 L H Propagation delay time, CLK or CLK INH to QHor QHtPL

44、H110/ CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 2.0 18.0 ns tPHL110/ CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 2.0 21.0 Propagation delay time, SH/LD to QHor QHtPLH210/ CL= 50 pF, see figure 4 All 4.5 V and 4.5 V 9, 10, 11 2.0 18.0 ns tPHL210/ CL= 50 pF, see figure 4 All 4.5

45、V and 5.5 V 9, 10, 11 2.0 21.0 Propagation delay time, H to QHtPLH310/ CL= 50 pF, see figure 4 All 4.5 V and 4.5 V 9, 10, 11 2.0 17.0 ns tPHL310/ CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 2.0 21.0 Propagation delay time, H to QHtPLH410/ CL= 50 pF, see figure 4 All 4.5 V and 4.5 V 9, 10,

46、11 2.0 18.0 ns tPHL410/ CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 2.0 20.0 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96559 DLA LAND AND MARITIME COLUMBUS, OHIO

47、 43218-3990 REVISION LEVEL D SHEET 8 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics Continued. Test Symbol Test conditions 1/ 2/ -55C TC +125C unless otherwise specified Device type VDDGroup A subgroups Limits 3/ Unit Min Max Maximum clock frequency fMAXCL= 50 pF, see figure

48、4 All 4.5 V and 5.5 V 9, 10, 11 71.0 MHz Setup time, SER before CLK or CLK INH ts1 CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 7.0 ns Setup time, CLK INH before CLK ts2CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 7.0 ns Setup time, data before SH/LD ts3CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 7.0 ns Setup time, SH/LD befo