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本文(DLA SMD-5962-96562 REV C-2012 MICROCIRCUIT DIGITAL ADVANCED CMOS RADIATION HARDENED SYNCHRONOUS 4-BIT UP DOWN BCD DECADE COUNTER MONOLITHIC SILICON.pdf)为本站会员(arrownail386)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA SMD-5962-96562 REV C-2012 MICROCIRCUIT DIGITAL ADVANCED CMOS RADIATION HARDENED SYNCHRONOUS 4-BIT UP DOWN BCD DECADE COUNTER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update boilerplate to MIL-PRF-38535 requirements. LTG 01-11-01 Thomas M. Hess B Correct title to more accurately describe the function. Update radiation features in section 1.5 and RHA paragraphs in section 4. Update the boilerplate paragraphs to

2、 current requirements as specified in MIL-PRF-38535. jak 10-01-20 Thomas M. Hess C Correct High and low level output voltage (VOHand VOL) test condition current (IOLand IOH) limits to table IA. Update the boilerplate paragraphs to current requirements as specified in MIL-PRF-38535. Delete class M re

3、quirements throughout MAA 12-12-18 Thomas M. Hess REV SHEET REV C C C C SHEET 15 16 17 18 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Larry T. Gauder DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil

4、 STANDARD MICROCIRCUIT DRAWING CHECKED BY Charles F.Saffle THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A APPROVED BY Monica L. Poelking MICROCIRCUIT, DIGITAL, ADVANCED CMOS, RADIATION HARDENED, SYNCHRONOUS 4-BIT UP/DOWN BCD DECADE COUNTER, MO

5、NOLITHIC SILICON DRAWING APPROVAL DATE 96-12-20 REVISION LEVEL C SIZE A CAGE CODE 67268 5962-96562 SHEET 1 OF 18 DSCC FORM 2233 APR 97 5962-E129-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96562 DLA LA

6、ND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes a

7、re available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example 5962 H 96562 01 V X C Federal RHA Device Device Case Lead stock class designato

8、r type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-)

9、indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 54ACS190 Radiation hardened, synchronous 4-bit up/down BCD decade counter 1.2.3 Device class designator. The device class designator is a sing

10、le letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outlines. The case outlines are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminal

11、s Package style E GDIP1-T16 or CDIP2-T16 16 Dual-in-line X CDFP4-F16 16 Flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DR

12、AWING SIZE A 5962-96562 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VDD) -0.3 V dc to +7.0 V dc DC input voltage range (VIN) -0.3 V dc to VDD+ 0.3 V dc DC output voltage range (VOUT) . -0.

13、3 V dc to VDD+ 0.3 V dc DC input current, any one input (IIN). 10 mA Latch-up immunity current (ILU) 150 mA Storage temperature range (TSTG) . -65C to +150C Lead temperature (soldering, 5 seconds) +300C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Junction temperature (TJ) +175C Maxi

14、mum package power dissipation (PD) . 1.0 W 1.4 Recommended operating conditions. 2/ 3/ Supply voltage range (VDD) +4.5 V dc to +5.5 V dc Input voltage range (VIN) +0.0 V dc to VDDOutput voltage range (VOUT). +0.0 V dc to VDDCase operating temperature range (TC) . -55C to +125C Maximum input rise and

15、 fall rate at VDD= 4.5 V (tr, tf) 1 ns/V 4/ 1.5 Radiation features. 5/ Maximum total dose available (dose rate = 50 300 rads (Si)/s) 1 x 106Rads (Si) Single event phenomenon (SEP) : No SEU occurs at effective LET (see 4.4.4.4) . 80 MeV/(mg/cm2) 6/ No SEL occurs at effective LET (see 4.4.4.4) . 120 M

16、eV/(mg/cm2) 6/ Dose rate induced upset (20 ns pulse) 1 x 109Rads (Si)/s 6/ Dose rate induced latch-up None 6/ Dose rate survivability 1 x 1012Rads (Si)/s 6/ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade pe

17、rformance and affect reliability. 2/ Unless otherwise noted, all voltages are referenced to VSS. 3/ The limits for the parameters specified herein shall apply over the full specified VDDrange and case temperature range of -55C to +125C unless otherwise noted. 4/ Derate system propagation delays by d

18、ifference in rise time to switch point for tror tf 1 ns/V. 5/ Radiation testing is performed on the standard evaluation circuit SEC. 6/ Limits are guaranteed by design or process, but not production tested unless specified by the customer through the purchase order or contract. Provided by IHSNot fo

19、r ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96562 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks.

20、The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATIONS MIL-PRF-38535 - Integrated Circuits Manufa

21、cturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard M

22、icrocircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this d

23、ocument to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation or contract. ASTM INTERNATIONAL (ASTM) ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradi

24、ation of Semiconductor Devices. (Copies of this document is available online at https:/www.astm.org/ or from ASTM International, P. O. Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959). JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JESD 20 - Standard for Description of 54/74ACXXX

25、X and 54/74ACTXXXX Advanced High-Speed CMOS Devices. (Copies of these documents are available online at http:/www.jedec.org/ or from JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240S, Arlington, VA 22201-2701.) 2.3 Order of precedence. In the event of a conflict between th

26、e text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. Provided by IHSNot for ResaleNo reproduction or networking permitted without

27、 license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96562 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-

28、38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions

29、 shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as speci

30、fied on figure 2. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.2.5 Switching waveforms and test circuits. The switching waveforms and test circuits shall be as specified on figure 4. 3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be maintained b

31、y the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics an

32、d postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are described in ta

33、ble IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the

34、device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-385

35、35. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to li

36、sting as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 sha

37、ll be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96562 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FOR

38、M 2234 APR 97 TABLE IA. Electrical performance characteristics. Test Symbol Test conditions 1/ 2/ -55C TC +125C unless otherwise specified Device type VDDGroup A subgroups Limits 3/ Unit Min Max High level input voltage VIHAll 4.5 V 1, 2, 3 3.15 V All 5.5 V 1, 2, 3 3.85 Low level input voltage VILAl

39、l 4.5 V 1, 2, 3 1.35 V All 5.5 V 1, 2, 3 1.65 High level output voltage VOHFor all inputs affecting output under test, VIN= VDDor VSSIOH= -100 A All 4.5 V 1, 2, 3 4.25 V Low level output voltage VOLFor all inputs affecting output under test, VIN= VDDor VSSIOL= 100 A All 4.5 V 1, 2, 3 0.25 V Input cu

40、rrent high IIHFor input under test, VIN= 5.5 V For all other inputs VIN= VDDor VSSAll 5.5 V 1, 2, 3 +1.0 A Input current low IILFor input under test, VIN= VSSFor all other inputs VIN= VDDor VSSAll 5.5 V 1, 2, 3 -1.0 A Quiescent supply current IDDQVIN= VDDor VSSAll 5.5 V 1, 2, 3 10.0 A Output current

41、 (Sink) IOL4/ VIN= VDDor VSS, VOL= 0.4 V All 4.5 V and 5.5 V 1, 2, 3 8.0 mA Output current (Source) IOH4/ VIN= VDDor VSS, VOH= VDD-0.4 V All 4.5 V and 5.5 V 1, 2, 3 -8.0 mA Short circuit output current IOS5/ 6/ VOUT= VDDand VSSAll 5.5 V 1, 2, 3 200 mA Input capacitance CINf = 1 MHz, see 4.4.1c All 0

42、.0 V 4 15.0 pF Output capacitance COUTf = 1 MHz, see 4.4.1c All 0.0 V 4 15.0 pF Switching power dissipation PSW7/ CL= 50 pF, per switching output All 4.5 V and 5.5 V 4, 5, 6 2.2 mW/MHz Functional test 8/ VIH= 0.7 VDD, VIL= 0.3 VDDSee 4.4.1b All 4.5 V and 5.5 V 7, 8 L H Propagation delay time, LOADto

43、 QXtPLH19/ CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 2.0 19.0 ns tPHL19/ CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 2.0 22.0 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT D

44、RAWING SIZE A 5962-96562 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics Continued. Test Symbol Test conditions 1/ 2/ -55C TC +125C unless otherwise specified Device type VDDGroup A subgroups Limits 3/ Un

45、it Min Max Propagation delay time, A, B, C, or D to QXtPLH29/ CL= 50 pF, see figure 4 All 4.5 V and 4.5 V 9, 10, 11 2.0 19.0 ns tPHL29/ CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 2.0 21.0 Propagation delay time, CLK to QXtPLH39/ CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 2.0 18

46、.0 ns tPHL39/ CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 2.0 20.0 Propagation delay time, CLK to RCOtPLH49/ CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 2.0 16.0 ns tPHL49/ CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 2.0 16.0 Propagation delay time, CLK to MAX/MIN tPLH5

47、9/ CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 2.0 18.0 ns tPHL59/ CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 2.0 23.0 Propagation delay time, D/Uto RCOtPLH69/ CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 2.0 16.0 ns tPHL69/ CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9

48、, 10, 11 2.0 18.0 Propagation delay time, D/Uto MAX/MIN tPLH79/ CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 1.0 14.0 ns tPHL79/ CL= 50 pF, see figure 4 All 4.5 V and 5.5 V 9, 10, 11 2.0 18.0 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STAND

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