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本文(DLA SMD-5962-96691 REV E-2011 MICROCIRCUIT MEMORY DIGITAL CMOS SRAM 128K x 8-BIT MONOLITHIC SILICON.pdf)为本站会员(eastlab115)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA SMD-5962-96691 REV E-2011 MICROCIRCUIT MEMORY DIGITAL CMOS SRAM 128K x 8-BIT MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added device type11. Change limits for ICCand ICCDR1in table I. 98-06-22 K. A. Cottongim B Add: note to paragraph 1.2.2 and table I, conditions. Add device types 12 through 17. Add vendor CAGE code 0EU86. Add condition D to paragraphs 4.2.a.1 and

2、 4.3.3.b.1. Changes to table I and dimensions to case outlines T, U, X, Y, and Z. Table I, add note 3 to CINand COUT. 01-03-01 Raymond Monnin C Add case outline N. 01-03-21 Raymond Monnin D Updated drawing to latest requirements. -sld 06-03-07 Raymond Monnin E Updated drawing paragraphs. -sld 11-07-

3、18 Charles F. Saffle REV SHEET REV E E E E E E E E E E E SHEET 15 16 17 18 19 20 21 22 23 24 25 REV STATUS REV E E E E E E E E E E E E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary Zahn DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil

4、 STANDARD MICROCIRCUIT DRAWING CHECKED BY Michael C. Jones THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Kendall A. Cottongim MICROCIRCUIT, MEMORY, DIGITAL, CMOS, SRAM, 128K x 8-BIT, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 96-10-30 AMSC N

5、/A REVISION LEVEL E SIZE A CAGE CODE 67268 5962-96691 SHEET 1 OF 25 DSCC FORM 2233 APR 97 5962-E371-11 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96691 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REV

6、ISION LEVEL E SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents five product assurance classes as defined in paragraph 1.2.3 and MIL-PRF-38534. A choice of case outlines and lead finishes which are available and are reflected in the Part or Identifying Number (PIN). When avail

7、able, a choice of radiation hardness assurance levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 - 96691 01 H X X Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1

8、.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 Radiation hardness assurance (RHA) designator. Device classes H and K RHA marked devices shall meet the MIL-PRF-38534 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Devi

9、ce type(s). The device type(s) shall identify the circuit function as follows: Device type 1/ 2/ Generic number Circuit function Access time 01 WMS128K8-120 SRAM, 128K X 8-bit 120 ns 02 WMS128K8-100 SRAM, 128K X 8-bit 100 ns 03 WMS128K8-85 SRAM, 128K X 8-bit 85 ns 04 WMS128K8-70 SRAM, 128K X 8-bit 7

10、0 ns 05 MT5C128K8-55, WMS128K8-55 SRAM, 128K X 8-bit 55 ns 06 MT5C128K8-45, WMS128K8-45 SRAM, 128K X 8-bit 45 ns 07 MT5C128K8-35, WMS128K8-35 SRAM, 128K X 8-bit 35 ns 08 MT5C128K8-25, WMS128K8-25 SRAM, 128K X 8-bit 25 ns 09 MT5C128K8-20, WMS128K8-20 SRAM, 128K X 8-bit 20 ns 10 MT5C128K8-17, WMS128K8

11、-17 SRAM, 128K X 8-bit 17 ns 11 WMS128K8-15 SRAM, 128K X 8-bit 15 ns 12 MT5C128K8-55L SRAM, 128K X 8-bit 55 ns 13 MT5C128K8-45L SRAM, 128K X 8-bit 45 ns 14 MT5C128K8-35L SRAM, 128K X 8-bit 35 ns 15 MT5C128K8-25L SRAM, 128K X 8-bit 25 ns 16 MT5C128K8-20L SRAM, 128K X 8-bit 20 ns 17 MT5C128K8-17L SRAM

12、, 128K X 8-bit 17 ns 1/ Due to the nature of the 4 transistor design of the die used in these device types, topologically pure testing is important, particularly for high reliability applications. The device manufacturer should be consulted concerning their testing methods and algorithms. 2/ Device

13、types and case outlines may be similar to the device types and case outlines listed on SMD 5962-89598. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96691 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REV

14、ISION LEVEL E SHEET 3 DSCC FORM 2234 APR 97 1.2.3 Device class designator. This device class designator shall be a single letter identifying the product assurance level. All levels are defined by the requirements of MIL-PRF-38534 and require QML Certification as well as qualification (Class H, K, an

15、d E) or QML Listing (Class G and D). The product assurance levels are as follows: Device class Device performance documentation K Highest reliability class available. This level is intended for use in space applications. H Standard military quality class level. This level is intended for use in appl

16、ications where non-space high reliability devices are required. G Reduced testing version of the standard military quality class. This level uses the Class H screening and In-Process Inspections with a possible limited temperature range, manufacturer specified incoming flow, and the manufacturer gua

17、rantees (but may not test) periodic and conformance inspections (Group A, B, C, and D). E Designates devices which are based upon one of the other classes (K, H, or G) with exception(s) taken to the requirements of that class. These exception(s) must be specified in the device acquisition document;

18、therefore the acquisition document should be reviewed to ensure that the exception(s) taken will not adversely affect system performance. D Manufacturer specified quality class. Quality level is defined by the manufacturers internal, QML certified flow. This product may have a limited temperature ra

19、nge. 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style N See figure 1 32 Co-fired ceramic flat pack, evolutionary pinout, with or without pedestal T See figure 1 32 Co-fired ceramic SOJ, evo

20、lutionary pinout U See figure 1 32 Co-fired ceramic SOJ, revolutionary pinout X See figure 1 36 Co-fired ceramic flat pack, revolutionary pinout, with or without pedestal and with or without non-conductive tie bar Y See figure 1 32 Co-fired ceramic dual-in-line, evolutionary pinout Z See figure 1 36

21、 Co-fired ceramic SOJ, revolutionary pinout 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38534. 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V dc to +7.0 V dc Signal voltage range (VG) -0.5 V dc to VCC+0.5 V dc Power dissipation (PD) . 0.88 W maximum Stor

22、age temperature range . -65C to +150C Lead temperature (soldering, 10 seconds) +300C 1.4 Recommended operating conditions. Supply voltage range (VCC) . +4.5 V dc to +5.5 V dc Input low voltage range (VIL) . -0.3 V dc to +0.8 V dc Input high voltage range (VIH) +2.2 V dc to VCC+ 0.3 V dc Case operati

23、ng temperature (TC) -55C to +125C 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from

24、 IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96691 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of

25、 this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATIONS MIL-PRF-38534 - Hybrid Microcircuits, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 -

26、 Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/a

27、ssist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precede

28、nce. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and K shall be in accordance with MIL-PRF-38534. Compli

29、ance with MIL-PRF-38534 shall include the performance of all tests herein or as designated in the device manufacturers Quality Management (QM) plan or as designated for the applicable device class. The manufacturer may eliminate, modify or optimize the tests and inspections herein, however the perfo

30、rmance requirements as defined in MIL-PRF-38534 shall be met for the applicable device class. In addition, the modification in the QM plan shall not affect the form, fit, or function of the device for the applicable device class. 3.2 Design, construction, and physical dimensions. The design, constru

31、ction, and physical dimensions shall be as specified in MIL-PRF-38534 and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). The truth

32、table(s) shall be as specified on figure 3. 3.2.4 Timing diagram(s). The timing diagram(s) shall be as specified on figures 4 and 5. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96691 DLA LAND AND MARITIME

33、 COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 5 DSCC FORM 2234 APR 97 3.2.5 Block diagram(s). The block diagram(s) shall be as specified on figure 6. 3.2.6 Output load circuit. The output load circuit used to test product shall be equivalent to the circuit specified on figure 7. 3.3 Electrical p

34、erformance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full specified operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specifi

35、ed in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers vendor similar PIN may also be marke

36、d. 3.6 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device described herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot sample, for each device type listed herein. Also,

37、the data should include a summary of all parameters manually tested, and for those which, if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer and be made available to the preparing activity (DLA Land and Maritime -VA) upon request. 3.7 Cert

38、ificate of compliance. A certificate of compliance shall be required from a manufacturer in order to supply to this drawing. The certificate of compliance (original copy) submitted to DLA Land and Maritime -VA shall affirm that the manufacturers product meets the performance requirements of MIL-PRF-

39、38534 and herein. 3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38534 shall be provided with each lot of microcircuits delivered to this drawing. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-

40、38534 or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 4.2 Screening. Screening shall be in accordance with MIL-PRF-38534. The following additional criteria shall apply: a. Burn-i

41、n test, method 1015 of MIL-STD-883. (1) Test condition B or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to either DLA Land and Maritime -VA or the acquiring activity upon request. Also, the test circuit shall specify t

42、he inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. (2) TAas specified in accordance with table 1 of method 1015 of MIL-STD-883. b. Interim and final electrical test parameters shall be as specified in table II

43、 herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96691 DLA LAND AND MARITIME COLUMBUS, OH

44、IO 43218-3990 REVISION LEVEL E SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ 2/ -55C TC+125C VSS= 0 V dc 4.5 V dc VCC 5.5 V dc unless otherwise specified Group A subgroups Device type Limits Unit Min Max DC parameters Operating supply curren

45、t ICC CS = VIL, OE = VIH, f = 5 MHz, VCC= 5.5 V dc 1,2,3 01-04 30 mA 05-17 150 Standby current ISB CS = OE = VIH, f = 5 MHz, VCC= 5.5 V dc 1,2,3 01,02 0.6 mA 03,04 1.0 05-08, 12-15 15 09-11, 16,17 20 Input leakage current ILIVIN= GND to VCC, VIL= 5.5 V dc 1,2,3 All 10 A Output leakage current ILOCS

46、= OE = VIH, VOUT= GND to VCC1,2,3 All 10 A Output low voltage VOLVCC= 4.5 V dc, IOL= 2.1 mA 1,2,3 01-07, 12-14 0.4 V VCC= 4.5 V dc, IOL= 8.0 mA 08-11, 15-17 0.4 Output high voltage VOHVCC= 4.5 V dc, IOH= -1 mA 1,2,3 01-07, 12-14 2.4 V VCC= 4.5 V dc, IOH= -4 mA 08-11, 15-17 2.4 Input low level voltag

47、e VIL1,2,3 All 0.8 V Input high level voltage VIH1,2,3 All 2.2 V Capacitance Input capacitance 3/ CINVIN= 0 V dc, f = 1.0 MHz, TA= +25C 4 All 20 pF Output capacitance 3/ COUTVIN= 0 V dc, f = 1.0 MHz, TA= +25C 4 All 20 pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or

48、networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96691 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ 2/ -55C TC+125C VSS= 0 V dc 4.5 V dc VCC 5.5 V dc unless otherwise specified Group A subgroups Device type Limits Unit Min Max Data retention characteristics. Data re

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