DLA SMD-5962-96734-1997 MICROCIRCUIT DIGITAL MIL-STD-1750 INSTRUCTION SET ARCHITECTURE MEMORY MANAGEMENT UNIT (MMU) MONOLITHIC SILICON《美军标1750指令系统体系机构内存管理硅单片电路数字微电路》.pdf

1、REVISIONSLTR DESCRIPTION DATE (YR-MO-DA) APPROVEDREV SHEETREVSHEET 15 16 17 19 20 21 22 23REV STATUSOF SHEETSREVSHEET 123456789101121314PMIC N/APREPARED BY Larry T. Gauder DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216 STANDARDMICROCIRCUITDRAWINGTHIS DRAWING IS AVAILABLEFOR USE BY ALLDEPARTMENT

2、SAND AGENCIES OF THEDEPARTMENT OF DEFENSEAMSC N/A CHECKED BYThomas M. HessMICROCIRCUIT, DIGITAL, MIL-STD-1750 INSTRUCTIONSET ARCHITECTURE, MEMORY MANAGEMENT UNIT(MMU), MONOLITHIC SILICONAPPROVED BYThomas M. HessDRAWING APPROVAL DATE97-07-16SIZEACAGE CODE672685962-96734REVISION LEVELSHEET 1 OF 23DSCC

3、 FORM 2233APR 97 5962-E222-97DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGDEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000SIZEA5962

4、-96734REVISION LEVEL SHEET2DSCC FORM 2234APR 971. SCOPE1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in th

5、e Part orIdentifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.1.2 PIN. The PIN is as shown in the following example:5962 - 96734 01 M X X G0DG0D G0D G0D G0D G0DG0DG0D G0D G0D G0D G0DG0D G0D G0D G0D G0D G0D Federal RHA Device Device

6、Case Lead stock class designator type class outline finishdesignator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3)/ Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and aremarked with the appropriate

7、 RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix Aspecified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.1.2.2 Device type(s). The device type(s) identify the circuit function as follows:Device type Generic nu

8、mber Circuit function01 BX1752 Memory management unit (MMU)1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level asfollows:Device class Device requirements documentationM Vendor self-certification to the requirements for MIL-STD-883 com

9、pliant,non-JAN class level B microcircuits in accordance with MIL-PRF-38535,appendix AQ or V Certification and qualification to MIL-PRF-385351.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:Outline letter Descriptive designator Terminals Package styleX CMGA

10、17-P101 101 Pin grid array packageY See figure 1 100 Gullwing-lead chip carrier package1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted

11、without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGDEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000SIZEA5962-96734REVISION LEVEL SHEET3DSCC FORM 2234APR 971.3 Absolute maximum ratings. 1/Supply voltage range (V ) . -0.7 V dc to +7.0 V dcDDInput voltage range (V ) -0.7 V dc to +7.0 V dcI

12、NStorage temperature range -65(C to +150(CMaximum power dissipation (P ) . 170 mW 2/DLead temperature (soldering, 10 seconds) +300(CThermal resistance, junction-to-case ( );JCCase outline X See MIL-STD-1835Case outline Y 10(C/WJunction temperature (T ) . +165(CJ1.4 Recommended operating conditions.S

13、upply voltage range (V ) . 4.5 V dc to 5.5 V dcDDMinimum high level input voltage (V );IHFCLK and STB inputs. 4.5 V dcRESETB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 V dc All other inputs 2.4 V dcMaximum low level input voltage (V );ILFCLK and STB inputs. 0

14、.5 V dcAll other inputs 0.8 V dcCase operating temperature range (T ) -55(C to +125(CCOperating frequency (FCLK max) . . . . . . . . . . . . . . . . . . . . . 40 MHz 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturinglogic tests (MIL-STD-883, test method

15、 5012) . . . . . . . . . . . . XX percent 3/2. APPLICABLE DOCUMENTS2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a partof this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are th

16、ose listed in theissue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in thesolicitation.SPECIFICATIONMILITARYMIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.STANDARDSMILITARYMIL-STD-883 - Test Methods and Proce

17、dures for Microelectronics.MIL-STD-973 - Configuration Management.MIL-STD-1835 - Microcircuit Case Outlines.1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at themaximum levels may degrade performance and affect reliability.2/ Must withstand

18、 the added P due to short circuit test (e.g., I ).DOS3/ Values will be added when they become available.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGDEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000SIZEA5962-96734

19、REVISION LEVEL SHEET4DSCC FORM 2234APR 97HANDBOOKSMILITARYMIL-HDBK-103 - List of Standard Microcircuit Drawings (SMDs).MIL-HDBK-780 - Standard Microcircuit Drawings.(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the StandardizationDocument Order

20、 Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text ofthis drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regul

21、ations unless aspecific exemption has been obtained.3. REQUIREMENTS3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. Themodifica

22、tion in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements fordevice class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specifiedherein.3.2 Design, construction, and physical dimensions. Th

23、e design, construction, and physical dimensions shall be as specified inMIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M.3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1.3.2.2 Terminal conne

24、ctions. The terminal connections shall be as specified on figure 2.3.2.3 Block diagram. The block diagram shall be as specified on figure 3.3.2.4 Switching waveforms. The switching waveforms shall be as specified on figure 4.3.3 Electrical performance characteristics and postirradiation parameter li

25、mits. Unless otherwise specified herein, theelectrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the fullcase operating temperature range.3.4 Electrical test requirements. The electrical test requirements shall be the subgroups

26、specified in table II. The electricaltests for each subgroup are defined in table I.3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also bemarked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not

27、feasible due to spacelimitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, theRHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Markingfor device class M shall be in

28、accordance with MIL-PRF-38535, appendix A.3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required inMIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A.3.6 Certificate of comp

29、liance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate ofcompliance shall be required from a manufacturer in order to be listed

30、as an approved source of supply in MIL-HDBK-103 (see6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for thisdrawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 andh

31、erein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGDEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000SIZEA5962-96734REVISION LEVEL SHE

32、ET5DSCC FORM 2234APR 973.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered tothis drawing.3.8 Notification of change for devi

33、ce class M. For device class M, notification to DSCC-VA of change of product (see 6.2herein) involving devices acquired to this drawing is required for any change as defined in MIL-STD-973.3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activi

34、ty retain theoption to review the manufacturers facility and applicable required documentation. Offshore documentation shall be madeavailable onshore at the option of the reviewer.3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be inmicroci

35、rcuit group number 105 (see MIL-PRF-38535, appendix A).Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGDEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000SIZEA5962-96734REVISION LEVEL SHEET6DSCC FORM 2234APR 97TABLE I.

36、 Electrical performance characteristics.Test Symbol Conditions 1/ -55(C T +125(CC4.5 V V 5.5 VDDunless otherwise specifiedGroup AsubgroupsDevicetypesLimits UnitsMin MaxLow level input voltage, FCLK and STB inputsVIL11, 2, 3 All 0.5 VLow level input voltage, all other inputsVIL21, 2, 3 All 0.8 VHigh

37、level input voltage, FCLK and STB inputsVIH11, 2, 3 All VDD-0.5VRESETB VIHR1, 2, 3 All 3.0 VHigh level input voltage, all other inputsVIH21, 2, 3 All 2.4 VLow level input current IILV = 5.5 V, V = 0.0 VDD IN1, 2, 3 All -75 AHigh level input current IIHV = 5.5 V, V = 5.5 VDD IN1, 2, 3 All -10 AOutput

38、 current, high impedance stateIOZV = 5.5 V, V = 5.5 VDD O1, 2, 3 All -10 AV = 5.5 V, V = 2.4 VDD O1, 2, 3 All 16 AV = 5.5 V, V = 0.5 VDD O1, 2, 3 All 70 ASupply current (dynamic) IDDOPV = 5.5 V, f = 40DD CLKMHz 1, 2, 3 All 60 mASupply current (Static) IDDV = 5.5 VDD1, 2, 3 All 7 mAInput capacitance,

39、 FCLK and STB inputsC ICT = +25(C, see 4.4.1dA4 All 11 pFInput capacitance, data bus inputsCID T = +25(C, see 4.4.1dA4 All 10 pFInput capacitance, all other inputsC IT = +25(C, see 4.4.1dA4 All 8.0 pFOutput capacitance C OT = +25(C, see 4.4.1dA4 All 8.0 pFFunctional tests See 4.4.1c 7, 8 AllAddress/

40、AS to valid PPA/XPPA bus delay timetAXSee figure 4 9, 10, 11 All 40 nsBus commands to PPA/XPPA bus delay timetBX9, 10, 11 All 25 nsAddress to valid data (I/O read) delay timetAD9, 10, 11 All 45 nsSTB setup time to FCLK tSF9, 10, 11 All 0 nsSee footnotes at end of table.Provided by IHSNot for ResaleN

41、o reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGDEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000SIZEA5962-96734REVISION LEVEL SHEET7DSCC FORM 2234APR 97TABLE I. Electrical performance characteristics - continued.Test Symbol Conditions 1/ -55(C T

42、 +125(CC4.5 V V 5.5 VDDunless otherwise specifiedGroup AsubgroupsDevicetypesLimits UnitsMin MaxSTB to XSTB delay time tSXSee figure 4 9, 10, 11 All 16 nsFCLK to XSTB delay timetFX9, 10, 11 All 21 nsDI, DTR, XBO, and IOM setup time to FCLKtBSU9, 10, 11 All 5 nsFCLK rise to QWEB delay timetFQ9, 10, 11

43、 All 25 nsFCLK fall to QWEB delay timetFBQ9, 10, 11 All 15 nsAddress/AS to IOMMUB delay timetAI9, 10, 11 All 41 nsBus commands to IOMMUB delay timetBI9, 10, 11 All 32 nsFCLK to MPROEB delay timetMP9, 10, 11 All 50 nsRESET/PTSB delay time to high impedance tRPZ9, 10, 11 All 22 nsNOP to high impedance

44、 (bus commands = 0) delay timetNZ9, 10, 11 All 21 nsData setup time to STB (I/O write)tDS9, 10, 11 All 5.0 nsData hold time to STB (I/O write)tDH9, 10, 11 All 5.0 nsATT2 setup time to XSTBtAT29, 10, 11 All 15 nsILLADDB/MPB setup time to QWEB falltIMQ9, 10, 11 All 20 nsATT4 setup time to XSTBtAT49, 1

45、0, 11 All 50 nsATT7 to FCLK setup timetAT79, 10, 11 All 0 nsATT7 delay time to PPA/XPPAtA7P9, 10, 11 All 20 nsAK bus setup time to FCLKt 2/AKF9, 10, 11 All 0 nsPEB setup time to XSTB tPX9, 10, 11 All 20 nsSee footnotes at end of table.Provided by IHSNot for ResaleNo reproduction or networking permit

46、ted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGDEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000SIZEA5962-96734REVISION LEVEL SHEET8DSCC FORM 2234APR 97TABLE I. Electrical performance characteristics - continued.Test Symbol Conditions 1/ -55(C T +125(CC4.5 V V 5.5 VDDunless other

47、wise specifiedGroup AsubgroupsDevicetypesLimits UnitsMin MaxPEB hold time to XSTB tPXHSee figure 4 9, 10, 11 All 0 nsILLADDB setup time to XSTBtIX9, 10, 11 All 20 nsILLADDB hold time to XSTBtIXH9, 10, 11 All 0 nsDMAK setup time to XSTB (to block)tDX9, 10, 11 All 20 nsMPROEB setup time to XSTBtMX9, 1

48、0, 11 All 15 nsDMAK hold time to XSTBtDMXH9, 10, 11 All 0 nsRDY setup time to FCLKtRF9, 10, 11 All 4.0 nsReset time tRESET9, 10, 11 All 50 nsAddress setup time to FCLKtASU9, 10, 11 All 0 ns1/ All voltage values are with respect to network ground terminal. For AC testing, the device shall be driven with V maximum ILand V minimum as specified in table I. Test conditions shall be worst case conditions unless otherwise specified.IH2/ Guaranteed to the limit specified