DLA SMD-5962-96772 REV C-2013 MICORCIRCUIT LINEAR 5 V 1394-1995 BACKPLANE TRANSCEIVER ARBITER MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add device type 02. Update boilerplate. -rrp 98-09-24 R. MONNIN B Replaced reference to MIL-STD-973 with reference to MIL-PRF-38535. gt 03-06-04 R. MONNIN C Update boilerplate paragraphs to current MIL-PRF-38535 requirements. Add paragraph 3.2.5.

2、 Delete references to device class M requirements. Add note to figure 4. - ro 13-01-28 C. SAFFLE REV SHEET REV C C C SHEET 15 16 17 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Rajesh Pithadia DLA LAND AND MARITIME COLUMBUS, OHIO 43

3、218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY Rajesh Pithadia APPROVED BY Raymond Monnin MICROCIRCUIT, LINEAR, 5 V, 1394-1995 BACKPLANE TRANSCEIVER/ARBITER, MONOLITHIC

4、 SILICON DRAWING APPROVAL DATE 96-10-24 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-96772 SHEET 1 OF 17 DSCC FORM 2233 APR 97 5962-E202-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96772 DLA L

5、AND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes

6、are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 96772 01 Q X A Federal stock class designator RHA designator (see 1.2.

7、1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-

8、) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 TSB14C01 5 V 1394-1995 backplane transceiver/arbiter 02 TSB14C01A 5 V 1394-1995 backplane transceiver/arbiter 1.2.3 Device class designator.

9、 The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outl

10、ine letter Descriptive designator Terminals Package style X See figure 1 68 Ceramic quad flat pack 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDAR

11、D MICROCIRCUIT DRAWING SIZE A 5962-96772 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VCC) -0.5 V dc to +6.0 V dc Input voltage range (VIN) -0.5 V dc to VCC+0.5 V dc Output voltage (VOUT) -0.5

12、 V dc to VCC+0.5 V dc Continuous total power dissipation at 25C . 1689 mW 3/ Operating free-air temperature range (TA) -55C to +125C Storage temperature range (TSTG) . -65C to +150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds +300C Thermal resistance, junction-to-case (JC) . 3C/W Th

13、ermal resistance, junction-to-ambient (JA) 74C/W 1.4 Recommended operating conditions. Supply voltage (VCC) 4.5 V dc to 5.25 V dc High level input voltage range (VIH): CMOS inputs . +0.7VCCTTL input . +2.0 V dc to VCCLow level input voltage range (VIL): CMOS inputs . +0.0 V dc to +0.2 VCCTTL input +

14、0.0 V dc to +0.8 V Input voltage range (VIN): CMOS / TTL +0.0 V dc to VCCHigh level output current (IOH): CMOS drivers +12.0 mA TTL drivers . +8.0 mA Low level output current (IOH): CMOS drivers +24 mA TTL drivers +8.0 mA Operating temperature range (TA) -55C to +125C _ 1/ Stresses above the absolut

15、e maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Design simulation was performed with a maximum operating junction temperature (TJ) = +150C. 2/ Unless otherwise noted, all voltages are referenced to GN

16、D. 3/ Above 25C, derate at a factor of 13.5 mW/C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96772 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 2. APPLIC

17、ABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTME

18、NT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-

19、103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order

20、 of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Ite

21、m requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 as specified herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described

22、 herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal conne

23、ctions. The terminal connections shall be as specified on figure 2. 3.2.3 Truth tables. The truth tables shall be as specified on figure 3. 3.2.4 Block diagram. The block diagram shall be as specified on figure 4. 3.2.5 Timing waveforms. The timing waveforms shall be as specified on figure 5. 3.3 El

24、ectrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical

25、test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962

26、-96772 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Test conditions -55C TA +125C 4.75 V VCC 5.25 V Device types Group A subgroups Limits Unit unless otherwise specified Min Max High level

27、output voltage VOHIOH= -4 mA, VCC= 4.5 V All 1,2,3 VCC - 0.8 V Low level output voltage VOLIOL= 4 mA, VCC= 5.25 V All 1,2,3 0.5 V High-level input current IIHVIN= VCCAll 1,2,3 1.0 A Low-level input current IILVIN= 0 V All 1,2,3 -1.0 A Off-state output current IOZVIN= 0 V or VCCAll 1,2,3 10 A Setup t

28、ime, D, CTL, LREQ low or high before SCLK high tsu 1/ TA= 25C, VCC= 5 V, see figure 5 All 9 7.0 ns Hold time, D, CTL, LREQ low or high after SCLK high th 1/ TA= 25C, VCC= 5 V, see figure 5 All 9 1.0 ns Delay time, SCLK high to D, CTL high or low td 1/ TA= 25C, VCC= 5 V, see figure 5 All 9 10.0 ns 1/

29、 If not tested, shall be guaranteed to the limits specified in table I herein. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitati

30、ons, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for de

31、vice classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The cert

32、ificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of

33、conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96772 DLA LAND A

34、ND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 Case X Symbol Dimensions Inches Millimeters Min Max Min Max A .134 .154 3.40 3.91 b .008 .013 0.20 0.33 c .005 .007 0.13 0.18 D 1.30 1.50 33.02 38.10 D1 .485 .500 12.32 12.70 D2 .400 BSC 10.16 BSC e .025 BSC 0.64 BS

35、C NOTE: The US government preferred system of measurement is the metric SI system. However, this item was originally designed using inch-pound units of measurement. In the event of conflict between the metric and inch-pound units, the inch-pound units shall take precedence. FIGURE 1. Case outline. P

36、rovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96772 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 Device type 01 and 02 Case outlines X Terminal number Termin

37、al symbol Terminal number Terminal symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VCCTI1 VCCGND VCCVCCPREFIX GND NC NC ARB_CLK PHYENA VCCENA_PRI VCCN_POR GND LREQ VCCSCLK TSCLK GND CTL0 CTL1 D0 D1 NC NC VCCEN_EXID EN_EXPRI EX_ID5 EX_ID4 EX_ID3 35

38、36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 EX_ID2 EX_ID1 EX_ID0 GND EX_PRI3 EX_PRI2 EX_PRI1 EX_PRI0 NC NC NC VCCPTEST_IDRV GND N_OEB_D GND TSTRB TDATA VCCRSTRB RDATA NC NC NC NC NC GND OSC_SEL GND XI_100 NC GND XI_50 NC FIGURE 2. Terminal conne

39、ctions. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96772 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 Terminal Name Type I/O Description ARB_CLK TTL O Ar

40、bitration clock. ARB_CLK is the clock used for arbitration. ARB_CLK is for test and debug. It can be put into a high-impedance state by PTEST_INDRV. This terminal is not used in normal operation and is always at 49.152 MHz. CTL0, CTL1 TTL I/O Control I/O. These are bidirectional signals that communi

41、cate between the transceiver/arbiter and the link that control passage of information between the two devices. D0, D1 TTL I/O Data I/O. These are bidirectional information signals that communicate between the transceiver/arbiter and the link. ENA_PRI TTL I Enable priority. ENA_PRI is tied low to ena

42、ble the 7-bit bus request. EN_EXID TTL I Enable external ID. When EN_EXID is asserted high, the ID for this node is set externally by EX_ID. When this terminal is tied/driven low, the source of the ID comes from the internal ID register. EN_EXPRI TTL I Enable external priority. When EN_EXPRI is asse

43、rted high (external priority enabled) the priority level for this node is set externally. This terminal should be tied low when not used. EX_ID5-EX_ID0 TTL I External ID. The ID for this node is determined by the value on the EX_ID terminals. Bit 0 is the MSB. EX_PRI3- EX_PRI0 TTL I External priorit

44、y. The priority for this node is determined by the value on the EX_PRI terminal. GND Supply - Circuit ground. LREQ TTL I Link request input. LREQ is an input from the link used by the link to signal the transceiver/arbiter of a request to perform some service. VCCSupply - Circuit power. NC - - Not c

45、onnected. N_OEB_D TTL O External driver enable. N_OEB_D is a negative active signal that enables the external driver for TDATA and TSTRB. N_POR TTL I Logic reset input. Forcing N_POR low causes a reset condition and resets the internal logic to the reset start state. FIGURE 2. Terminal connections -

46、 continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96772 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 9 DSCC FORM 2234 APR 97 Terminal Name Type I/O Description OSC_SEL VCC/

47、 GND I Select clock frequency. OSC_SEL should be pulled up to VCCwhen the operating frequency is 50 MHz. When the operating frequency is 100 MHz then it should be pulled to ground. It should not be left floating. PHYENA TTL O Phy enable. When the phy is driving it is low, PHYENA is the control to th

48、e CTL0, CTL1, D0, and D1 drivers. PHYENA is for test and debug. It can be put into a high-impedance state by PTEST_INDRV. This terminal is not used in normal operation. PTEST_INDRV TTL I Test output enable. PTEST_INDRV enables/disables the drivers to the test terminals ARB_CLK, PHYENA, and RPREFIX. During normal operation, PTEST_INDRV should be tied to VCCto disable the drivers. RDATA TTL I Receive data. Incoming data is received at the data rate. RPREFIX TTL O Receive prefix. When asserted high (enabled), RP