DLA SMD-5962-97523 REV B-2008 MICROCIRCUIT MEMORY DIGITAL CMOS PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON《单片硅可编程逻辑阵列CMOS数字存储器微电路》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update drawing to current requirements. Editorial changes throughout. - gap 02-05-10 Raymond Monnin B Boilerplate update, part of 5 year review. ksr 08-08-05 Robert M. Heber REV B B SHET 35 36 REV B B B B B B B B B B B B B B B B B B B B SHEET 15

2、16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth S. Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218-3990 htt

3、p:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Raymond Monnin AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 97-07-31 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67

4、268 5962-97523 SHEET 1 OF 36 DSCC FORM 2233 APR 97 5962-E462-08 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97523 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FOR

5、M 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (P

6、IN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 97523 01 Q X X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see

7、1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified

8、 RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 4010E-4 10000 gate programmable array 4 ns 1.2.3 Device

9、 class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-P

10、RF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA8-P191 191 1/ Pin grid array package Y see figure 1 196 Quad f

11、lat package Z see figure 1 196 Quad flat package 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. _ 1/ 191 = actual number of pins used, not maximum listed in MIL-STD-1835. Provided by IHSNot for ResaleNo

12、reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97523 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 2/ Supply voltage range to ground potential (VCC) .

13、-0.5 V dc to +7.0 V dc DC input voltage range . -0.5 V dc to VCC+0.5 V dc Voltage applied to three-state output (VIS) -0.5 V dc to VCC+0.5 V dc Maximum power 2.0 W Thermal resistance, junction-to-case (JC): Case outline X . See MIL-STD-1835 Case outlines Y and Z . 20C/W 3/ Junction temperature (TJ)

14、+150C 4/ Lead temperature (soldering, 10 seconds) +260C Storage temperature range . -65C to +150C 1.4 Recommended operating conditions. 5/ Case operating temperature range (TC) -55C to +125C Supply voltage relative to ground (VCC) . +4.5 V dc minimum to +5.5 V dc maximum Ground voltage (GND) . 0 V d

15、c 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contrac

16、t. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOK

17、S MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-50

18、94.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation. ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standard EIA/JESD78 - IC Latch-Up

19、 Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. Th

20、ese documents also may be available in or through libraries or other informational services.) _ 2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 3/ When a thermal resistanc

21、e for this case is specified in MIL-STD-1835 that value shall supersede the value indicated herein. 4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 5/ All voltage values in this draw

22、ing are with respect to VSS. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97523 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2.3 Order of preceden

23、ce. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requiremen

24、ts. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein.

25、The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-3

26、8535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Logic blo

27、ck diagram. The logic block diagram shall be as specified on figure 3. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and s

28、hall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2

29、 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall stil

30、l be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in M

31、IL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this d

32、rawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supp

33、ly for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required fo

34、r device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) in

35、volving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentatio

36、n. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo rep

37、roduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97523 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditions 4.5 V

38、VCC 5.5 V -55C TC +125C unless otherwise specified Group A subgroups Devicetype Min Max Unit High level output voltage VOHVCC= 4.5 V, IOH= -4.0 mA 1, 2, 3 01 2.4 V Low level output voltage 1/ VOLVCC= 5.5 V, IOL= 12 mA, 1, 2, 3 01 0.4 V Quiescent LCA supply current 2/ ICCOVCC= VIN= 5.5 V 1, 2, 3 01 5

39、0 mA Input leakage current IILVIN= 0 V and 5.5 V, VCC= 5.5 V 1, 2, 3 01 -10 +10 A Pad pull-up current (when selected) IRINVIN= 0 V 1, 2, 3 01 -0.02 -0.25 mA Horizontal long line pull-up current (when selected) IRLLAt logic low 1, 2, 3 01 0.2 2.5 mA Input capacitance CINVCC= 5.0 V, f = 1 Mhz, VIN= 0

40、to 5 V, see 4.4.1e 4 01 16 pF Output capacitance COUTVCC= 5.0 V, f = 1 Mhz, VOUT= 0 to 5 V, see 4.4.1e 4 01 16 pF Functional test FT see 4.4.1c 7, 8A, 8B 01 Tpid+ 20*Tilo+ Int. + Tops+ rtd tB199.1 Tpid+ 20*Thho+ Int. + Tops+ rtd tB2119.1 Tpid+ 20*Tiho+ Int. + Tops+ rtd tB3139.1 Tpid+ 20*Trio+ Int. +

41、 Tops+ rtd tB4173.1 Tcko+ Int. + Tick tB510.1 Tcko+ Int. + Thhck tB611.1 Tcko+ Int. + Tdick tB79.1 Tcko+ Int. + Tihck tB812.2 Tcko+ Int. + Tecck tB99, 10, 11 01 10.1 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-ST

42、ANDARD MICROCIRCUIT DRAWING SIZE A 5962-97523 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Limits Test Symbol Conditions 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Gr

43、oup A subgroups Device type Min Max Unit Interconnect + tpid+ tops+ topcy+ tsum- tBYPtB10197.7 Interconnect + tpid+ tops+ tascy+ tsum- tBYPtB11245 Interconnect + tpid+ tops+ tincy+ tsumtB12107.4 Interconnect + tpid+ tops+ tincy + tsum + tBYPtB139, 10, 11 01 43.5 ns WIDE DECODER SWITCHING CHARACTERIS

44、TICS Full length, both pull-ups inputs from IOB I-pins TWAF4/ 15 Full length, both pull-ups inputs from internal logic TWAFL4/ 18 Half length, one pull-up inputs from IOB I-pins TWAO4/ 16 Half length, one pull-up inputs from internal logic TWAOLSee figures 3 and 4 as applicable. 3/ 4/ 01 18 ns CLB S

45、WITCHING CHARACTERISTICS Combinatorial delay F/G inputs to X/Y outputs TILO5/ 6/ 3.9 Combinatorial delay F/G inputs via H to X/Y outputs TIHO5/ 6/ 5.9 Combinatorial delay C inputs via H to X/Y outputs THHO5/ 01 4.9 ns CLB fast carry logic operand inputs (F1,F2,G1, G4) to COUTTOPCY6/ 4.4 CLB fast car

46、ry logic add/ subtract input (F3) to COUTTASCYSee figures 3 and 4, as applicable. 6/ 6.8 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97523 DEFENSE SUPPLY CENTER COLUMBUS COL

47、UMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. - continued. Limits Test Symbol Conditions 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A subgroups Device type Min Max Unit CLB SWITCHING CHARACTERISTICS - Contin

48、ued. CLB fast carry logic initialization inputs (F1,F3) to COUTTINCY6/ 2.9 CLB fast carry logic CINthrough function generators to X/Y outputs TSUM6/ 5 CLB fast carry logic CINto COUT, bypass function generators TBYP6/ 1 Sequential delays clock K to outputs Q TCKO5/ 6/ 5 Set-up time before clock K, F/G inputs TICK5/ 6/ 4 Set-up time before clock K, F/G inputs via H TIHCK5/ 6/ 6.1 Set-up time before clock K, C inputs via H1 THHCK5/ 6/ 5 Set-up time before clock K, C inputs via DIN TDICK5/ 6/ 3 Set-up time before