DLA SMD-5962-97606 REV G-2013 MICROCIRCUIT DIGITAL DIGITAL SIGNAL PROCESSOR MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Updated boilerplate to include class N. Added case outline X. Editorial changes throughout. TMH 98-01-27 Monica L. Poelking B Changes in accordance with NOR 5962-R043-99. 99-03-04 Monica L. Poelking C Added junction temperature to paragraph 1.3.

2、Made technical change to supply current in table I. LTG 00-01-28 Monica L. Poelking D Update boilerplate to MIL-PRF-38535 requirements. LTG 01-04-13 Thomas M. Hess E Change VDD, VIN, VOUT, PD, JCin section 1.3. Make following changes to table I: Change VDDfor IZ; delete IICtest; change ICC limit; de

3、lete VDDfor CIN, COUT, CX; change td6, td30, tw6, td33, twlimits; delete footnote 2/. Correct signal names in figures 3 and A-1. Change RESET and TIMER PIN TIMINGS waveforms. Add SHZ TIMING waveform. Add application note to section 6. Editorial changes throughout. TVN 02-02-26 Thomas M. Hess F Updat

4、e boilerplate to current MIL-PRF-38535 requirements. CFS 07-12-05 Thomas M. Hess G Update boilerplate to current MIL-PRF-38535 requirements. PHN 13-05-06 Thomas M. Hess REV G G SHEET 35 36 REV G G G G G G G G G G G G G G G G G G G G SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 R

5、EV STATUS OF SHEETS REV G G G G G G G G G G G G G G SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Thomas M. Hess DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGEN

6、CIES OF THE DEPARTMENT OF DEFENSE AMSC N/A CHECKED BY Thomas M. Hess APPROVED BY Monica L. Poelking MICROCIRCUIT, DIGITAL, DIGITAL SIGNAL PROCESSOR, MONOLITHIC SILICON DRAWING APPROVAL DATE 97-08-04 REVISION LEVEL G SIZE A CAGE CODE 67268 5962-97606 SHEET 1 OF 36 DSCC FORM 2233 APR 97 5962-E388-13 P

7、rovided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 SIZE A 5962-97606 REVISION LEVEL F SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents three pr

8、oduct assurance class levels consisting of space application (device class V), high reliability (device classes Q), and nontraditional performance environment (device class N). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When a

9、vailable, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. For device class N, the user is cautioned to assure that the device is appropriate for the application environment. 1.2 PIN. The PIN is as shown in the following example: 5962 - 97606 01 N X X Federal stock clas

10、s designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes N, Q, and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with

11、the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Devi

12、ce type Generic number Circuit function 01 320LC31 Digital signal processor 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation N Certification and qualification to MIL-PRF-38

13、535 with a nontraditional performance environment (encapsulated in plastic) Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835, JEDEC Publication 95, and as follows: Outline letter Descriptive designator Terminals Pack

14、age style Document X See figure 1 132 Plastic quad flatpack JEP 95 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes N, Q, and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license

15、from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-97606 REVISION LEVEL G SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range (VDD) . -0.3 V dc to +5.0 V dc DC input voltage range (VIN) . -0.3 V dc to +5.0 V dc DC

16、 output voltage range (VOUT) -0.3 V dc to +5.0 V dc Continuous power dissipation (PD) 3/ . 850 mW Storage temperature range (TSTG) . -65C to +150C Junction temperature (TJ): Die code 9 +125C Case outline X +150C Thermal resistance, junction to case (JC): Case outline X 11.0C/W 1.4 Recommended operat

17、ing conditions. Supply voltage range (VDD) . +3.13 V dc to +3.47 V dc Supply voltage range (CVSS, etc.) (VSS) . 0 V dc nominal High-level input voltage range (VIH): 4/ (except RESET ) +1.8 V dc to VDD+ 0.3 V dc For RESET . +2.2 V dc to VDD+ 0.3 V dc Low-level input voltage range (VIL) 4/ . -0.3 V dc

18、 to 0.6 V dc Maximum high-level output current (IOH) . -300 A Maximum low-level output current (IOL) . +2 mA CLKIN high level input voltage (VTH) 4/ +2.5 V dc to VDDto +0.3 V dc Case operating temperature range (TC) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and h

19、andbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circui

20、ts, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 -

21、Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094). _ 1/ Stresses above the absolute maximum rating may cause permanen

22、t damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ All voltage values are with respect to VSS. 3/ Actual operating power is less. This value was obtained under specially produced worst-case test conditions which are not sustained durin

23、g normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern to both primary and expansion buses at the maximum rate possible. 4/ Maximum VIH, minimum VILand maximum VTH are not production tested. Provided by IHSNot for ResaleNo reproduction or networki

24、ng permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-97606 REVISION LEVEL G SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herei

25、n. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEP 95 - Registered and Standard Outlines for Semiconductor Devices (Copies of this document are available online at www.jedec.org/ or from J

26、EDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S, Arlington, VA 22201). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, super

27、sedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes N, Q, and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Qua

28、lity Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix A to this document. 3.2 Design, construction, and physical dimensions. The design, construction,

29、and physical dimensions for device classes N, Q, and V shall be as specified in MIL-PRF-38535 and herein. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 herein and on figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Block

30、 diagram. The block diagram shall be as specified on figure 3. 3.2.4 Switching waveforms and test circuit. The switching waveforms and test circuit shall be as specified on figure 4. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, t

31、he electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical t

32、ests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the op

33、tion of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes N, Q, and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes N, Q, and V sha

34、ll be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. A certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6 herein). The certificate of compliance submitted to DLA Land and Mariti

35、me -VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535 shall be provided with each lot of microc

36、ircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 SIZE A 5962-97606 REVISION LEVEL G SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical perf

37、ormance characteristics. Test Symbol Test conditions -55C TC +125C 1/ unless otherwise specified VDDGroup A subgroups Limits Unit Min Max High level output voltage VOHIOH= -300 A 3.13 V 1, 2, 3 2.0 V Low level output voltage VOLIOL= 2 mA 3.13 V 1, 2, 3 0.4 Three-state current IZ3.47 V 1, 2, 3 -20 20

38、 A Input current IIFor input under test VIN= VSSto VDD3.13 V to 3.47 V 1, 2, 3 -10 +10 Input current with internal pull-ups 2/ IIP3.13 V to 3.47 V 1, 2, 3 -600 +10 Supply current 3/ ICCTA= 25C, fx= 40 MHz 3.47 V 1, 2, 3 300 mA Input capacitance CINTC= +25C, See 4.4.1b 4 15 pF Output capacitance COUT

39、4 20 X2/CLKIN capacitance CX4 25 Functional testing See 4.4.1d 7, 8 Fall time, CLKIN 4/ tf1X2/CLKIN timing See figure 4 9, 10, 11 5 ns Pulse duration, CLKIN low tw1tC1= 25 ns 9 Pulse duration, CLKIN high tw2tC1= 25 ns 9 Rise time, CLKIN 4/ tr15 Cycle time, CLKIN tc125 303 Fall time, H1/H3 tf2H1/H3 t

40、iming See figure 4 3 Pulse duration, H1/H3 low tw3P = tC1P-5 Pulse duration, H1/H3 high tw4P = tC1P-6 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43

41、218-3990 SIZE A 5962-97606 REVISION LEVEL G SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test conditions -55C TC +125C 1/ unless otherwise specified Group A subgroups Limits Unit Min Max Rise time, H1/H3 tr2H1/H3 timing See figure 4 9, 10, 11

42、 3 ns Delay time, from H1(H3) low to H3(H1) high 5/ td10 4 Cycle time, H1/H3 tc250 606 Delay time, from H1 low to STRB low 5/ td2Memory ( STRB = 0) See figure 4 9, 10, 11 0 6 ns Delay time, from H1 low to STRB high 5/ td30 6 Delay time, from H1 high to R/ W low 5/ td40 9 Delay time, from H1 low to A

43、 valid 5/ td60 10 Setup time, D valid before H1 low (read) tsu114 Hold time, D after H1 low (read) 5/ th10 Setup time, RDY before H1 high tsu38 Hold time, RDY after H1 high th20 Delay time, H1 high to R/ W high (write) td89 Valid time, D after H1 low (write) tv117 Hold time, D after H1 high (write)

44、th30 Delay time, form H1 high to A valid on back-to-back write cycles td915 Delay time, from RDY to A valid 4/ td117 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME CO

45、LUMBUS, OHIO 43218-3990 SIZE A 5962-97606 REVISION LEVEL G SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Test conditions -55C TC +125C 1/ unless otherwise specified Group A subgroups Limits Unit Min Max Delay time, H3 high to XF0 low td17Timin

46、g for XF0 and XF1 when executing LDFI or LDII See figure 4 9, 10, 11 13 ns Set-up time, XF1 valid after H1 low tsu710 Hold time, XF1 after H1 low th70 Delay time, from H3 high to XF0 high td18Timing for XF0 when executing a STFI or STII See figure 4 9, 10, 11 13 ns Delay time, from H3 high to XF0 lo

47、w td19Timing for XF0 and XF1 when executing a SIGI See figure 4 9, 10, 11 13 ns Delay time, from H3 high to XF0 high td2013 Set-up time, XF1 valid before H1 low tsu810 Hold time, XF1 after H1 low th80 Valid time, H3 high to XF tv3Timing for loading XF register when conformed as an output pin See fig

48、ure 4 9, 10, 11 13 ns Hold time, XF after H3 high 4/ th9Change of XF from output to input mode See figure 4 9, 10, 11 13 ns Setup time, XF before H1 low tsu910 Hold time, XF after H1 low th100 Delay time, from H3 high to XF switching from input to output td21Change of XF from input to output mode See figure 4 9, 10, 11 17 ns Setup time, for RESET before CLKIN low 4/ tsu10RESET timing See figure 4 9, 10, 11 10 P ns Delay time, from CLKIN high to H1 high td222 14 Delay time, from CLKIN high to H1 low td232 14 Setup time, RESET high before H1 low and aft