DLA SMD-5962-97608 REV B-2005 MICROCIRCUIT DIGITAL CMOS 32-BIT RISC MICROPROCESSOR MONOLITHIC SILICON《微型电路 数字型 CMOS 32位RISC微处理器 单块硅》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add device types 05, 06,07, 08, and 09. Editorial changes throughout. TVN 00-06-13 Monica L. Poelking B Update boilerplate to MIL-PRF-38535 requirements. - CFS 05-10-04 Thomas M. Hess REV SHEET REV B B B B B B B B B B B B B B B B B B SHEET 15 16

2、17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 REV B B B B B B B B B B B B B B REV STATUS OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Thanh V. Nguyen CHECKED BY Thomas M. Hess DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil APPROVED BY Monic

3、a L. Poelking DRAWING APPROVAL DATE 98-04-22 MICROCIRCUIT, DIGITAL, CMOS, 32-BIT RISC MICROPROCESSOR, MONOLITHIC SILICON SIZE A CAGE CODE 67268 5962-97608 STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A REVISION LE

4、VEL B SHEET 1 OF 32 DSCC FORM 2233 APR 97 5962-E406-05 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-97608 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 AP

5、R 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When

6、 available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 97608 01 Q X X Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator

7、(see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA le

8、vels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 PC603E-80 32-bit RISC microprocessor 02 PC603E-100 32-bit RISC microproces

9、sor 03 PC603E-120 32-bit RISC microprocessor 04 PC603E-133 32-bit RISC microprocessor 05 PC603R-166 32-bit RISC microprocessor 06 PC603R-200 32-bit RISC microprocessor 07 PC603R-233 32-bit RISC microprocessor 08 PC603R-266 32-bit RISC microprocessor 09 PC603R-300 32-bit RISC microprocessor 1.2.3 Dev

10、ice class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MI

11、L-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 240 Ceramic leaded chip carrier Y See figure 1 255

12、 Ceramic column grid array 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-97608 STANDARD MICR

13、OCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Core supply voltage range (VCC): Device types 01 - 04 -0.3 V dc to +4.0 V dc Device types 05 - 09 -0.3 V dc to +2.75 V dc PLL supply voltage range

14、 for device types 05 - 09 (AVCC). -0.3 V dc to +2.75 V dc I/O supply voltage range for device types 05 - 09 (OVCC) -0.3 V dc to +3.6 V dc DC input voltage range (VIN) -0.3 V dc to +5.5 V dc Maximum power dissipation at (PD): Device types 01 - 04 5.3 W Device types 05 - 09 6.0 W Storage temperature r

15、ange (TSTG) . -55C to +150C Lead temperature for device types 01 - 04 (soldering, 10 seconds). +300C Thermal resistance, junction-to-case (JC): Device types 01 - 04 2.2C/W Device types 05 - 09 0.1C/W Thermal resistance, junction-to-column for device types 05 - 09 (JS) 3.7C/W 1.4 Recommended operatin

16、g conditions. Core supply voltage range (VCC): Device types 01 - 04 +3.135 V dc to +3.465 V dc Device types 05 - 09 +2.375 V dc to +2.625 V dc PLL supply voltage range for device types 05 - 09 (AVCC). +2.375 V dc to +2.625 V dc I/O supply voltage range for device types 05 - 09 (OVCC) +3.135 V dc to

17、+3.465 V dc Logic high input voltage range (VIH): Device types 01 - 04 2.4 V dc to 5.5 V dc Device types 05 - 09 2.0 V dc to 5.5 V dc Logic low input voltage range (VIL). GND to 0.8 V dc System clock input high voltage (CVIH) 2.4 V dc to 5.5 V dc System clock input low voltage (CVIL) GND to 0.4 V dc

18、 Minimum high level output voltage (VOH) . 2.4 V dc Maximum low level output voltage (VOL) 0.4 V dc Frequency of operation (fOP): Device type 01 . 80 MHz Device type 02 . 100 MHz Device type 03 . 120 MHz Device type 04 . 133 MHz Device type 05 . 166 MHz Device type 06 . 200 MHz Device type 07 . 233

19、MHz Device type 08 . 266 MHz Device type 09 . 300 MHz Case operating temperature range (TC). -55C to +125C Maximum operating junction temperature (TJ): Device types 01 - 04 +137C Device types 05 - 09 +126C Minimum operating case temperature (TC) -55C 1/ Stresses above the absolute maximum rating may

20、 cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-97608 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLU

21、MBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified,

22、the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface

23、 Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil o

24、r from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those c

25、ited in the solicitation. INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS (IEEE) IEEE Standard 1149.1 - IEEE Standard Test Access Port and Boundary Scan Architecture. (Copies of these documents are available from the Institute of Electrical and Electronics Engineers, 445 Hoes Lane, Piscataway, NJ

26、08854-4150.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3

27、. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit,

28、 or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZ

29、E A 5962-97608 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein

30、for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Block diagram. The block

31、diagram shall be as specified on figure 3. 3.2.4 Timing waveforms. The timimg waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiatio

32、n parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking.

33、The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA produ

34、ct using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device class

35、es Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufactur

36、er in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSC

37、C-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of confo

38、rmance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification

39、to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufact

40、urers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-385

41、35, appendix A). 3.11 IEEE 1149.1 compliance interface. The boundary-scan interface of the device is a fully compliant implementation of the IEEE 1149.1 standard. 3.11.1 Test access port. The device has five dedicated JTAG signals which are described in the following table. The TDI and TDO scan port

42、s are used to scan instructions as well as data into the various scan registers for JTAG operations. The scan operation is controlled by the test access port (TAP) controller which in turn is controlled by the TMS input sequence. The scan data is latched in at the rising edge of TCK. Provided by IHS

43、Not for ResaleNo reproduction or networking permitted without license from IHS-,-,-SIZE A 5962-97608 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 IEEE interface pin descriptions Signal name Input/Output Weak pul

44、lup provided IEEE 1149.1 function TDI Input Yes Serial scan input signal TDO Output No Serial scan output signal TMS Input Yes TAP controller mode signal TCK Input Yes Scan clock TRST Input Yes TAP controller reset TRST is a JTAG optional signal which is used to reset the TAP controller asynchronous

45、ly. The TRST signal assures that the JTAG logic does not interfere with the normal operation of the chip, and can be asserted coincident with the HRESET . 3.11.2 TAP controller. The TAP (Tap Access Port) controller is a state machine that controls the JTAG scan protocol. The TAP controller implement

46、s 16 states specified by the IEEE 1149.1 specification. The TAP controller state machine is clocked by TCK and the state transitions are controlled by the TMS input. 3.11.3 JTAG instructions. The device supports the three required JTAG instructions: BYPASS, SAMPLE/PRELOAD, and EXTEST which are contr

47、olled by an 8-bit instruction register. These instructions are scanned in serially (LSB first) via the TDI pin. The table of the JTAG instructions for the device is given below. JTAG instructions Instruction Encoding Test data register accessed BYPASS 11111111 Bypass register SAMPLE/PRELOAD 11000000

48、 Boundary-scan register EXTEST 00000000 Boundary-scan register The BYPASS instruction. The bypass register contains a single shift-register stage and is used to provide a minimum-length serial path between the TDI and the TDO pins of a component when no test operation of that component is required.

49、This allows more rapid movement of test data to and from other components on a board that are required to perform test operations. The SAMPLE/PRELOAD instruction. The mandatory SAMPLE/PRELOAD instruction allows a snapshot of the normal operation of the component to be taken and examined. It also allows data values to be loaded onto