DLA SMD-5962-97631 REV A-2013 MICROCIRCUIT MEMORY CMOS 32K X 9 PARALLEL SYNCHRONOUS FIFO MONOLITHIC SILICON.pdf

1、 REVISIONS LTR DESCRIPTION DATE APPROVED A Updated drawing to reflect current MIL-PRF-38535 requirements. - glg 13-05-29 Charles Saffle REV SHEET REV A A A A A A A A SHEET 15 16 17 18 19 20 21 22 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PRE

2、PARED BY Gary L. Gross DLA LAND AND MARITIME STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY All DEPARTMENTS APPROVED BY Raymond Monnin MICROCIRCUIT, MEMORY, CMOS, 32K X 9 PARALLEL SYNCHRONOUS, FIF

3、O, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 98 09 11 AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-97631 SHEET 1 OF 22 DSCC FORM 2233 APR 97 5962-E405-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-

4、,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97631 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device

5、 class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 97631 01 Q X A

6、 Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and a

7、re marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Clock cycle Device type Generic number 1/ Circuit function time (min) 01 32K X 9 CMOS parallel synchronous FIFO 15 ns 1.2.3 Device

8、class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835, an

9、d as follows: Outline letter Descriptive designator Terminals Package style X CQCC1-N32 32 Rectangular leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. 1.3 Absolute maximum ratings. 2/ Terminal voltage with respect to ground . -0.5

10、 V dc to +7.0 V dc DC output current . 20 mA Storage temperature range -65C to +150C Maximum power dissipation (PD) 1.25 W Lead temperature (soldering, 10 seconds) . +260C Thermal resistance, junction-to-case (JC): Case X See MIL-STD-1835 Junction temperature (TJ) . +175C 1/ Generic numbers are also

11、 listed on the Standard Microcircuit Drawing Source Bulletin at the end of this document and will also be listed in MIL-HDBK-103 and QML-38535. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97631 DLA LAND A

12、ND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. Supply voltage (VCC) . +4.5 V dc to +5.5 V dc Supply voltage (GND). 0 V Minimum high level input voltage (VIH) . 2.2 V dc minimum Maximum low level input voltage (VIL) . +0.8 V

13、dc minimum Case operating temperature range (TC) . -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of

14、 these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Ele

15、ctronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil/ or from the Standardization Document Order Desk, 700 Ro

16、bbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. JEDEC INTE

17、RNATIONAL (JEDEC) JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to the JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107; http:/www.jedec.org.) 2.3 Order of precedence. In the event of a conflict between the text of thi

18、s drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3/ Stresses above the absolute maximum ratings may cause permanent damage to the device.

19、Extended operation at the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97631 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A

20、SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QM

21、L) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as do

22、cumented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A “Q“ or “QML“ certification mark in accordance with MIL-PRF-38

23、535 is required to identify when the QML flow option is used. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 h

24、erein and on figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table. The truth table shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristi

25、cs are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall

26、 be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking t

27、he “5962-“ on the device. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved

28、source of supply in MIL-HDBK-103 and QML-38535 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements h

29、erein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DLA Land and Maritime-VA shall be required for any change tha

30、t affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of th

31、e reviewer. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97631 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics

32、. Test Symbol Conditions -55C TC+125C 4.5 V VCC 5.5 V unless otherwise specified Group A subgroups Device types Limits Unit Min Max Input leakage current ILI0.4 V VIH, 0.4 V the minimum limit, tFRL(max) = tCLK+ tSKEW2. When tSKEW2the minimum limit specified in table I, tFRL(maximum) = tCLK+ tSKEW2.

33、When tSKEW2 the minimum limit, tFRL(maximum) = either 2tCLK+ tSKEW2or tCLK+ tSKEW2. The latency timing applies only at the empty boundary ( EF = LOW). 8. If a write is performed on this rising edge of the write clock, there will be Full-(m-1) words in the FIFO when PAF goes low. 9. 32768 - m words.

34、10. tSKEW2is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during the current clock cycle. If the time between the rising edge of RCLK and the rising edge of WCLK is less than t , then PAF may not change state until the next WCLK edge. 11. PAE offset = n. 12. t

35、SKEW2is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change state during the clock cycle. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then PAE may not change state until the next RCLK rising edge. 13. If a read is perf

36、ormed on this rising edge of the read clock, there will be Empty+n-1 words in the FIFO when PAE goes low. 14. The first word is available the cycle after EF goes HIGH, always. 15. PAF offset = m. FIGURE 4. Timing waveforms - continued. Provided by IHSNot for ResaleNo reproduction or networking permi

37、tted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97631 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 20 DSCC FORM 2234 APR 97 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535,

38、 appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition D. The test circ

39、uit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified

40、 in method 1015 of MIL-STD-883. (2) TA= +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table IIA herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. 4.3 Quality conformance inspection. Qualit

41、y conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table IIA herein. b. Subgroups 5 and 6 in table I, method 5005 of MI

42、L-STD-883 shall be omitted. c. Subgroup 4 (CINand COUT measurement) shall be measured only for the initial test and after any design or process changes which may affect capacitance. Sample size is 15 devices with no failures, and all input and output terminals tested. d. O/V (latch-up) tests shall b

43、e measured only for initial qualification and after any design or process changes which may affect the performance of the device. For device classes Q and V, the procedures and circuits shall be under the control of the device manufacturers TRB in accordance with MIL-PRF-38535 and shall be made avai

44、lable to the preparing activity or acquiring activity upon request. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be considered destructive. Information contained in JESD 78 may be used for reference. e. Subgroups 7 and 8 tests shall include verification of th

45、e truth table. 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table IIA herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition D. The test circuit shall be maintained by the manufacturer under document revision leve

46、l control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. (2) TA= +125C, minimum. (3) Test duratio

47、n: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-97631 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL A SHEET 21 DSCC FORM 223

48、4 APR 97 TABLE IIA. Electrical test requirements. 1/, 2/, 3/, 4/, 5/, 6/, 7/ Line No. Test Requirements Subgroups (per MIL-PRF-38535, table III) Device class Q Device class V 1 Interim electrical parameters (see 4.2) 1, 7, 9 1, 7, 9 2 Static burn-in I method 1015 Not required Required 3 Same as line 1 1*, 7* 4 Dynamic burn-in (method 1015) Required Required 5 Same as line 1 1*, 7* 6 Final electrical parameters 1*, 2, 3, 7*, 8A, 8B, 9, 10, 11 1*, 2, 3, 7*, 8A, 8B, 9, 10, 11 7 Group A test requirements 1, 2, 3, 4*, 7,