DLA SMD-5962-98644 REV B-2012 MICROCIRCUIT MEMORY DIGITAL CMOS SOI RADIATION- HARDENED 32K x 8-BIT MASK PROGRAMMABLE ROM MONOLITHIC SILICON.pdf

1、 DSCC FORM 2233 APR 97 5962-E091-13 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Boilerplate update and part of five year review. tcr 06-01-13 Raymond Monnin B Update drawing to reflect current requirements. glg 12-11-27 Charles Saffle REV SHEET REV B B B B B B B SHEET 15 16 17 18 19 20 21 R

2、EV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary L. Gross DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling THIS DRAWING IS AVAILABLE FOR USE BY A

3、LL DEPARTMENTS APPROVED BY Raymond Monnin MICROCIRCUIT, MEMORY, DIGITAL, CMOS, SOI, RADIATION- HARDENED, 32K x 8-BIT MASK PROGRAMMABLE ROM, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 98-09-03 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-98644 SHEET 1

4、OF 21 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98644 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two produc

5、t assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels

6、are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 H 98644 01 Q Z C_ | | | | | | | | | | | | | | | | | | Federal RHA Device Device Case Lead stock class designator type class outline finish designator (1.2.1) (See 1.2.2) designator (See 1.2.4) (See 1.2.5) / (See 1.

7、2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appr

8、opriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number 1/ Circuit function Input buffer type Access time 01 6656 32K X 8-bit radiation hardened mask PROM CMOS 25 ns 02 6656 32K

9、 X 8-bit radiation hardened mask PROM TTL 25 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(

10、s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style Y See figure 1 28 Flat Package Z See figure 1 36 Flat Package 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V 1/ Gene

11、ric numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this document and will also be listed in QML-38535 and MIL-HDBK-103 (see 6.6 herein). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIR

12、CUIT DRAWING SIZE A 5962-98644 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 2/ Supply voltage range (VDD) -0.5 V dc to +6.5 V dc Voltage on any pin with respect to ground . -0.5 V dc to VDD+0.5 V dc DC output current (IO

13、UT) . 25 mA Maximum power dissipation (PD) . 2.5 W Lead temperature (soldering, 10 seconds maximum) +270C Thermal resistance, junction-to-case (JC): Case Z 2.0C/W Junction temperature (TJ) +175C Storage temperature range -65C to +150C Data retention 10 years (minimum) 1.4 Recommended operating condi

14、tions. Supply voltage (VDD) +4.5 V dc to +5.5 V dc Ground voltage (VSS) . 0.0 V dc Case operating temperature range (TC) . -55C to +125C Radiation features: Total dose irradiation, (Dose Rate = 50 to 300 Rads (Si)/S) . 1.0 MRads(Si) Single event phenomenon (SEP) effective linear energy threshold (LE

15、T) with no upsets . 120 MEV-cm2/mg Neutron irradiation 1 x 1014neutrons/cm23/ 1.5 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) . 100% 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and hand

16、books. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits,

17、 Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard For Microcircuit Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings (SMDs). MIL-HDBK-780 -

18、Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2/ Stresses above the absolute maximum rating may cause permanent dama

19、ge to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 3/ Guaranteed, but not tested. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98644 DLA LAND AND MAR

20、ITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the so

21、licitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192-00 - Standard Guide for the Measurement of Single Event Phenomena Induced by Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO

22、Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959; http:/www.astm.org.) JEDEC INTERNATIONAL (JEDEC) JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to the JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107;

23、 http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a c

24、onflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item

25、 requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, constructio

26、n, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal conne

27、ctions shall be as specified on figure 2. 3.2.3 Truth table. The truth table for unprogrammed devices shall be as specified on figure 3. 3.2.4 AC test circuit and timing characteristics. The ac test circuit and timing characteristics shall be as specified on figure 4. 3.2.5 Read cycle waveforms. The

28、 read cycle waveforms shall be as specified on figure 5. 3.2.6 Radiation exposure circuit. The radiation exposure circuit shall be as specified on figure 6. 3.2.7 Data retention. A data retention stress test shall be completed as part of the vendors reliability monitors. This test shall be done for

29、initial characterization and after any design or process changes which may affect data retention. The methods and procedures may be vendor specific but shall guarantee data retention as specified in paragraph 1.3 over the full military temperature range. The vendors procedure shall be kept under doc

30、ument control and shall be made available upon request of the acquiring or preparing activity, along with test data. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98644 DLA LAND AND MARITIME COLUMBUS, OHIO

31、43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.3 AID requirements. The following items shall be provided to the device manufacturer by the customer as part of an AID. These items form a part of the manufacturers design database/database archive and shall be maintained under document rev

32、ision level control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. As such, these items will not appear in the AID in the traditional sense. 3.3.1 ROM mask definition. To gene

33、rate a mask for a ROM code, an ASCII file shall be submitted to the device manufacturer per paragraph 3.3. The format for the code shall be as follows: a. Two fields, address followed by data in hexadecimal code, most significant bit to least significant bit (AH is most significant bit). b. Addresse

34、s need not be in order. c. Address and data fields must be separated by at least one space or a slash “/“. d. A semicolon “;“ may terminate the line, but is not required. e. No “end-of-file“ characters are required. f. Comments are preceded by the pound sign “#“. g. Comments may be on the same line

35、AFTER address and data fields. h. Unused locations do not need to be addressed, but MUST be specified as all zeroes or all ones. This can be done as a comment. 3.3.2 Fault coverage measurement of manufacturing logic tests. 3.3.3 Burn-in circuit. 3.3.4 Radiation exposure circuit. 3.3.5 Maximum device

36、 cross section for SEP. 3.3.6 Programmed devices. The truth table for final masked (programmed) devices shall be as specified in the altered item drawing. 3.4 Electrical performance characteristics and post-irradiation parameter limits. Unless otherwise specified herein, the electrical performance c

37、haracteristics and post-irradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.5 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup ar

38、e defined in table I. 3.6 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “

39、5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. The AID PIN shall be marked on the part and shall be in addition to the required marking of MIL-PRF-38535. 3.6.1 Certificat

40、ion/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.7 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the require

41、ments of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein.

42、 3.8 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD

43、 MICROCIRCUIT DRAWING SIZE A 5962-98644 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions -55C TC +125C 4.5 V VDD 5.5 V unless otherwise specified Group A subgroups Device type Limits

44、 Unit Min Max Output low voltage VOL1VDD= 4.5 V, IOL= 10 mA 1, 2, 3 All 0.4 V M,D,P,L,R,F,G,H 1 1/ 2/ VOL2VDD= 4.5 V, IOL= 200A 1, 2, 3 All 0.15 V M,D,P,L,R,F,G,H 1 1/ 2/ Output high voltage VOH1VDD= 4.5 V, IOH= -200A 1, 2, 3 All VDD- 0.1 V M,D,P,L,R,F,G,H 1 1/ 2/ VOH2IOH= -5.0mA 1, 2, 3 All 4.2 M,D

45、,P,L,R,F,G,H 1 1/ 2/ Input low voltage CMOS inputs VIL1VDD= 4.5 V 1, 2, 3 01 0.3 x VDDV M,D,P,L,R,F,G,H 1 1/ 2/ Input low voltage TTL inputs VIL2VDD= 4.5 V 1, 2, 3 02 0.8 V M,D,P,L,R,F,G,H 1 1/ 2/ High-level input voltage CMOS inputs VIH1VDD= 5.5 V 1, 2, 3 01 0.7 x VDDV M,D,P,L,R,F,G,H 1 1/ 2/ High-

46、level input voltage TTL inputs VIH2VDD= 5.5 V 1, 2, 3 02 2.2 V M,D,P,L,R,F,G,H 1 1/ 2/ Input leakage current IILK0 V VIN 5.5 V 1, 2, 3 All -5 5 A M,D,P,L,R,F,G,H 1 1/ 2/ 2/ Three-state output leakage current IOLK0 V VOUT 5.5 V Output = high Z 1, 2, 3 All -10 10 A M,D,P,L,R,F,G,H 1 1/ 2/ 2/ See footn

47、otes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98644 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions -55C TC +125C 4.5 V VDD 5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max Input capacitance 2/ 3/ CINVIN= VDDor VSS, f = 1 MHz See 4.4.1c 4 All 9 pF Output capacitance 2/ 3/ COUTVOUT= VDDor VSS, f = 1 M