DLA SMD-5962-99514 REV C-2012 MICROCIRCUIT MEMORY DIGITAL CMOS 1-MEG X 1-BIT SERIAL CONFIGURATION PROM MONOLITHIC SILICON.pdf

1、REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes to Figure 1. Terminal connections. ksr 01-09-04 Raymond Monnin B Boilerplate update and part of five year review. tcr 06-01-13 Raymond Monnin C Update drawing to reflect current requirements. glg 12-11-27 Charles Saffle REV SHEET REV SHEET

2、 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary Gross DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling THIS DRAWING IS AVAILABLE FOR USE BY AL

3、L DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Raymond Monnin MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 1-MEG X 1-BIT SERIAL CONFIGURATION PROM, MONOLITHIC SILICON DRAWING APPROVAL DATE 99-07-14 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-99514 SHEET 1 OF 14 DSCC FORM 2233

4、APR 97 5962-E097-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99514 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing docume

5、nts three product assurance class levels consisting of space application (device class V), high reliability (device class Q), and nontraditional performance environment (device class N). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PI

6、N). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. For device class N, the user is cautioned to assure that the device is appropriate for the application environment. 1.2 PIN. The PIN shall be as shown in the following example: 5962 - 99514 01 N X X |

7、 | | | | | | | | | | | | | | | | | Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes N, Q, and V RHA marked devices meet the MI

8、L-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device types shall identify the circuit function as follows: Device type Generic number 1/ Circuit function 01 XQ1701L 1-MEG X 1-bit PROM 1.2.3 Device c

9、lass designator. The device class designator shall be a single letter identifying the product assurance level as follows: Device class Device requirements documentation N Certification and qualification to MIL-PRF-38535 with a non-traditional performance environment encapsulated in plastic Q or V Ce

10、rtification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835, JEDEC Publication 95, and as follows: Outline letter Descriptive designator Terminals Package style X PDSO-G-20 20 Small outline integrated circuit (plastic) (JEDEC MS-013-AC)

11、 Y GQCC1-J44 44 J-leaded quad chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes N, Q, and V or MIL-PRF-38535, appendix A for device class M. _ 1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of t

12、his document and will also be listed in MIL-HDBK-103. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99514 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.3 A

13、bsolute maximum ratings. 2/ Supply voltage range to ground potential (VCC) . -0.5 V dc to +4.0 V dc Supply voltage relative to ground (VPP) -0.5 V dc to + 12.5 V dc Input voltage with respect to ground -0.5 V dc to VCC+ 0.5 V dc Voltage applied to three state output . -0.5 V dc to VCC+ 0.5 V dc Lead

14、 temperature (soldering, 10 seconds) +260C Thermal resistance, junction-to-case (JC) . See MIL-STD-1835 Case X 36C/W Case Y 10.2C/W Junction temperature (TJ) +150C Storage temperature range (TSTG) . -65C to +150C Data retention 10 years, minimum 1.4 Recommended operating conditions. Supply voltage r

15、ange (VCC) +3.0 V dc minimum to +3.6 V dc maximum Ground voltage (GND) . 0 V dc Input high voltage (VIH) . 2.0 V dc to VCCInput low voltage (VIL) . 0 V dc to 0.8 V dc Case operating temperature range (TC) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. T

16、he following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufac

17、turing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard For Microcircuit Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microc

18、ircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following documents form a part of this document

19、 to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192-00 - Standard Guide for the Measurement of Single Event Phenomena Induced by Heavy

20、 Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959; http:/www.astm.org.) 2/ Stresses above the absolute maximum rating may cause permanent damage to

21、the device. Extended operation at the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99514 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVIS

22、ION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 JEDEC INTERNATIONAL (JEDEC) JESD 78 - IC Latch-Up Test. (Applications for copies should be addressed to the JEDEC Solid State Technology Association, 3103 North 10th Street, Suite 240-S, Arlington, VA 22201-2107; http:/www.jedec.org.) (Non-Government standar

23、ds and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and t

24、he references cited herein, the text of this drawing shall take precedence. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes N, Q, and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Mana

25、gement (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes N, Q, and V. 3.

26、2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed

27、devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in screening (see 4.2 herein) or qualification conformance inspection, groups A, B, or C (see 4.4), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percent of t

28、he total number of cells shall be programmed or at least 25 percent of the total number of cells to any altered item drawing. 3.2.3.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.3 Electrical performance characteristics and p

29、ostirradiation parameter limits. Unless otherwise specified, the electrical performance characteristics, and post-irradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirement

30、s shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is n

31、ot feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes N, Q, and V shall be in accordance with MIL-PRF-38535. 3.5.1 Certification/complianc

32、e mark. The certification mark for device classes N, Q, and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes N, Q, and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements

33、 of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes N, Q, and V, the requirements of MIL-PRF-38535. 3.7 Certifi

34、cate of conformance. A certificate of conformance as required for device classes N, Q, and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Data retention. A data retention stress test shall be completed as part of the vendors reliability monitors. T

35、his test shall be done for initial characterization and after any design or process change which may affect data retention. The methods and procedures may be vendor specific, but shall guarantee the number of years listed in section 1.3 herein over the full military temperature range. The vendors pr

36、ocedure shall be kept under document control and shall be made available upon request of the acquiring or preparing activity, along with test data.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99514 DLA LAN

37、D AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. See footnotes at end of table. Test Symbol Conditions 3.0 V VCC 3.6 V -55C TC +125C unless otherwise specified Group A subgroups Limits Unit Min Max Power supply c

38、urrent ICCCLK = Max 1,2,3 10 mA Standby current ISB1,2,3 50 A Input leakage current IILVIN= GND or VCC1,2,3 10 A Output leakage current IOZVOUT= GND or VCC1,2,3 10 A Input low voltage VIL1,2,3 0 0.8 V Input high voltage VIH1,2,3 2.0 VCCV Output low voltage VOLIOL= 3 mA 1,2,3 0.4 V Output high voltag

39、e VOHIOH= -3 mA 1,2,3 2.4 V Output capacitance COUTf = 1.0 MHz, VOUT= 0 V see 4.4.1e 1/ 4 10 pF Input capacitance CINf = 1.0 MHz, VIN= 0 V see 4.4.1e 1/ 4 10 pF Functional tests see 4.4.1c 7, 8A,8B Clock frequency fCKSee figures 3 and 4 as applicable 9,10,11 15 MHz Clock period tCK9,10,11 67 ns CLK

40、low time 2/ tLC9,10,11 25 ns CLK high time 2/ tHC9,10,11 25 ns Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99514 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR

41、 97 TABLE I. Electrical performance characteristics - Continued. 1/ CINand COUTare periodically sampled and not 100-percent tested but shall be guaranteed to the limits specified in table I. 2/ These parameters are guaranteed by periodic characterization. 3/ Float delays are measured with minimum te

42、ster AC load. Test Symbol Conditions 3.0 V VCC 3.6 V -55C TC +125C unless otherwise specified Group A subgroups Limits Unit Min Max OE to data delay tOESee figures 3 and 4 as applicable. 9,10,11 30 ns CE to data delay tCE9,10,11 45 ns CE or OE to data float delay 3/ tDF 9, 10, 11 50 ns CE setup time

43、 to CLK tSCE9,10,11 25 ns CE hold time to CLK 2/ tHCE9,10,11 0 ns Data hold time from CE , OE , or CLK tOH9,10,11 0 ns CLK to data delay tCAC9,10,11 45 ns OE high time tHOE9,10,11 25 ms CLK to CEO delay tOCK9,10,11 30 ns CLK to data float delay 3/ tCDF9,10,11 50 ns CE to CEO delay tOCE9,10,11 35 ns

44、RESET/ OE to CEO delay tOOE9,10,11 30 ns Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99514 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 Device Type All Ca

45、se outline X Y Pin name Terminal number 1/ DATA 1 2 CLK 3 5 RESET/OE (OE/ RESET ) 8 19 CE 10 21 GND 11 24 these tests shall have been fault graded in accordance with MIL-STD-883, method 5012 (see 1.5 herein). d. O/V (latch-up) tests shall be measured only for initial qualification and after any desi

46、gn or process changes which may affect the performance of the device. For device classes Q and V, the procedures and circuits shall be under the control of the device manufacturers TRB in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or acquiring activity upon r

47、equest. Testing shall be on all pins, on five devices with zero failures. Latch-up test shall be considered destructive. Information contained in JESD78 may be used for reference. e. Subgroup 4 (CINand COUTmeasurements) shall be measured only for initial qualification and after any process or design

48、 changes which may affect input or output capacitance. Capacitance shall be measured between the designated terminal and GND at a frequency of 1 MHz. Sample size is 5 devices with no failures, and all input and output terminals tested. (1) The following shall apply to device class N only. Sample size is five devices with no failures. For CINand COUTa device manufacturer may qualify devices by functional groups. A specific fun