DLA SMD-5962-99540 REV A-2002 MICROCIRCUIT DIGITAL-LINEAR 10-BIT 20 MSPS PARALLEL OUTPUT CMOS ANALOG-TO-DIGITAL CONVERTER MONOLITHIC SILICON《微型电路 数字线型 10位20MSPS并联输出CMOS 模数转化器 单块硅》.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Drawing updated to reflect current requirements. - gt 02-05-10 Raymond Monnin REV SHET REV A SHET 15 REV STATUS REV A A A A A A A A A A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENT

2、ER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY RAJESH PITHADIA COLUMBUS, OHIO 43216 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY RAYMOND MONNIN MICROCIRCUIT, DIGITAL-LINEAR, 10-BIT, 20 MSPS PARALLEL OUTPUT CMOS, AND AGENCIES OF THE DEPARTMENT OF DEFEN

3、SE DRAWING APPROVAL DATE 99-04-08 ANALOG-TO-DIGITAL CONVERTER, MONOLITHIC SILICON AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 67268 5962-99540 SHEET 1 OF 15 DSCC FORM 2233 APR 97 5962-E380-02 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.Provided by IHSNot for Resal

4、eNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99540 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents three product assurance class level

5、s consisting of space application (device class V), high reliability (device classes M and Q), and traditional performance environment (device class N). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Ra

6、diation Hardness Assurance (RHA) levels are reflected in the PIN. For device class N, the user is cautioned to assure that the device is appropriate for the application environment. 1.2 PIN. The PIN is as shown in the following example: 5962 - 99540 01 N X X Federal stock class designator RHA design

7、ator (see 1.2.1) Devicetype (see 1.2.2) Device class designator Caseoutline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes N, Q, and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA desig

8、nator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Ci

9、rcuit function 01 TLC876 10-bit, 20 MSPS parallel output CMOS analog-to-digital converter 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to th

10、e requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A N Certification and qualification to MIL-PRF-38535 with a nontraditional performance environment (encapsulated in plastic) Q or V Certification and qualification to MIL-PRF-3853

11、5 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style Document X MS-013 AE 28 Plastic small outline JEDEC Publication 95 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for devi

12、ce classes N, Q, and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99540 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 3

13、DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage, AVDDto AGND, DVDDto DGND-0.3 V to +6.5 V Reference voltage input range to AGND, VI(REFTF), VI(REFBF), VI(REFBS), VI(REFTS)-0.3 V to AVDD+ 0.3 V Analog input voltage range to AGND.-0.3 V to AVDD+ 0.3 V Digital input voltage range.

14、-0.3 V to DVDD+ 0.3 V Digital output voltage range applied from external source -0.5 V to DVDDPower dissipation (PD).319.69 mW 2/ Operating virtual junction temperature range (TJ)-55C to +150C Storage temperature range .-65C to +150C Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds+260C

15、Thermal resistance, junction-to-case (JC) 15.4C/W Thermal resistance, junction-to-ambient (JA) .78.2C/W 1.4 Recommended operating conditions. Supply voltage (VS): AVDD+4.5 V to +5.25 V 3/ DVDD+4.5 V to 5.25 V 3/ DRVDD.+3 V to +5.25 V Reference input voltage (top), (VI(REFT).VI(REFB)+ 1 to 4.5 V Refe

16、rence input voltage (bottom), (VI(REFB).0 V to VI(REFT) 1 V Analog input voltage, (VI(AIN).1 VPPminimum High level input voltage (VIH): With DRVDDat 3 V 2.4 V With DRVDDat 5 V 4 V With DRVDDat 5.25 V .4.2 V Low level input voltage (VIL): With DRVDDat 3 V 0.6 V With DRVDDat 5 V 1 V With DRVDDat 5.25

17、V .1.05 V Pulse duration, clock high tW(CLKH) .23 ns Pulse duration, clock low tW(CLKL) .23 ns Ambient operating temperature (TA)-55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this dra

18、wing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-3853

19、5 - Integrated Circuits, Manufacturing, General Specification for. 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Derating factor is 12.78 mW/C. 3/ The voltage differe

20、nce between AVDDand DVDDterminals cannot exceed 0.5 V to maintain performance specification. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99540 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVI

21、SION LEVEL A SHEET 4 DSCC FORM 2234 APR 97 STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Sta

22、ndard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following documents form a p

23、art of this document to the extent specified herein. Unless otherwise specified, the issues of the documents which are DoD adopted are those listed in the issue of the DODISS cited in the solicitation. Unless otherwise specified, the issues of documents not listed in the DODISS are the issues of the

24、 documents cited in the solicitation. ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Publication 95 - Registered and Standard Outlines for Semiconductor Devices. (Applications for copies should be addressed to the Electronics Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834). (No

25、n-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text o

26、f this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device c

27、lasses N, Q, and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device c

28、lass M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes N, Q, and

29、V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Logic diagram(s). The logic diagram(s) shall be as specifie

30、d on figure 2. 3.2.4 Timing diagram(s). The timing diagram(s) shall be as specified on figure 3. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as

31、specified in table I and shall apply over the full ambient operating temperature range. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99540 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION

32、LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Power supply section Operating supply current IDDAVDD2/ 1,2,3 01 25 mA DVDD2/ 5 DRVDD100 A Power

33、 dissipation PD1,2,3 01 150 mW Standby power PDSBSTBY pin = high, CLK running 1,2,3 01 85 mW STBY pin = high, CLK inhibited at VDDor 0 V 35 Digital inputs section High-level input current IIHDVDD= 5 V 1,2,3 01 -10 +10 A Low-level input current IILDVDD= 5 V 1,2,3 01 -50 +50 A Low-level input current,

34、 CLK IIL(CLK) DVDD= 5 V 1,2,3 01 -10 +10 A Logic outputs section High-level output voltage VOHIOH= 50 A, DRVDD= 3 V 1,2,3 01 2.4 V IOH= 50 A, DRVDD= 5 V 3.8 IOH= 0.5 mA, DRVDD= 5 V 2.4 Low-level output voltage VOLIOL= 50 A, DRVDD= 3.6 V 1,2,3 01 0.7 V IOL= 50 A, DRVDD= 5.25 V 1.05 IOL= 0.6 mA, DRVDD

35、= 5.25 V 0.4 High-impedance-state output current IOZ1,2,3 01 -10 +10 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99540 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-

36、5000 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max DC accuracy section Differential nonlinearity DNL 3/ 1,2,3 01 1 LSB Refe

37、rence input section Reference input resistance RREF1,2,3 01 350 750 Dynamic performance section Effective number of bits ENOB fIN= 3.58 MHz 4/ 4 01 8 Bits Signal-to-total harmonic distortion+noise S / THD+N fIN= 3.58 MHz 4/ 4 01 50 dB Total harmonic distortion THD fIN= 3.58 MHz 4/ 4 01 -56 dB Timing

38、 requirements section Maximum conversion rate fCONV5/ 9,10,11 01 20 MHz Delay time, output tdOCL= 20 pF 9,10,11 01 5 ns Delay time, pipeline, latency tdpipe9,10,11 01 3.5 Clock cycles Disable time, OE to high Z tdisDDCL= 20 pF 9,10,11 01 15 ns Enable time, OE to valid data tenHLCL= 20 pF 9,10,11 01

39、15 ns 1/ Unless otherwise specified, AVDD= DVDD= 5 V, DRVDD= 3.3 V, VI(REFT)= 3.6 V, VI(REFB)= 1.6 V, and fCLK= 20 MSPS. 2/ The voltage difference between AVDDand DVDDterminals cannot exceed 0.5 V to maintain performance specification. 3/ A differential nonlinearity error of less than 1 LSB ensures

40、no missing codes. 4/ The voltage difference between AVDDand DVDDcannot exceed 0.5 V to maintain performance specification. At input clock rise times less than 20 ns, the offset full-scale error increases approximately by a factor of (20 / tr)0.5where trequals the actual rise time in nanoseconds. 5/

41、The conversion rate can be a minimum of 10 kHz without degradation in specified performance. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99540 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVI

42、SION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 Device type 01 Case outline X Terminal number Terminal symbol 1 AGND 2 DRVDD3 D04 D15 D2 6 D37 D48 D5 9 D610 D711 D8 12 D913 DRGND 14 DGND 15 CLK 16 OE 17 STBY18 DVDD19 AGND20 DGND 21 REFTS 22 REFTF 23 NC 24 REFBF 25 REFBS 26 CML 27 AIN 28 AVDDFIGURE 1. Ter

43、minal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99540 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 8 DSCC FORM 2234 APR 97 Terminal symbol I / O Descripti

44、on AGND - Analog ground AIN I Analog input AVDD- 5 V analog supply CLK I Clock input CML O Bypass for an internal bias point. Typically a 0.1 F capacitor minimum is connected from this terminal to ground. DGND - Digital ground DVDD- 5 V digital supply DRVDD- 3.3 V / 5 V digital supply. Supply for di

45、gital input and output buffers. DRGND - 3.3 V / 5 V digital ground. Ground for digital input and output buffers. D0-D9 O Digital date out. D0:LSB, D9:MSB OE I Output enable. When OE = low or NC, the device is in normal operating mode. When OE = high, D0-D9 are high impedance. REFBF I Reference botto

46、m force. REFBS I Reference bottom sense. REFTF I Reference top force. REFTS I Reference top sense. STBY I Standby enable. When STBY = low or NC, the device is normal operating mode. When STBY = high, the device is in standby mode. FIGURE 1. Terminal connections Continued. Provided by IHSNot for Resa

47、leNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99540 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 9 DSCC FORM 2234 APR 97 NOTE: Sample and hold amplifier. FIGURE 2. Logic diagram. Provided by IHSNot

48、for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99540 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 10 DSCC FORM 2234 APR 97 FIGURE 3. Timing diagrams. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99540 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 11 DSCC FORM 2234 APR 97 FIGURE