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本文(DLA SMD-5962-99576 REV C-2003 MICROCIRCUIT DIGITAL-LINEAR DUAL 12-BIT PROGRAMMABLE DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL VOLTAGE REFERENCE MONOLITHIC SILICON《微型电路 数字线型 参考内部压力的双.pdf)为本站会员(花仙子)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

DLA SMD-5962-99576 REV C-2003 MICROCIRCUIT DIGITAL-LINEAR DUAL 12-BIT PROGRAMMABLE DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL VOLTAGE REFERENCE MONOLITHIC SILICON《微型电路 数字线型 参考内部压力的双.pdf

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Drawing updated to reflect current requirements. gt 02-07-03 R. Monnin B Make change to power supply current test maximum limits as specified under table I. - ro 03-08-05 R. Monnin C Make change to VIHand VILlimits as specified under paragraph 1.

2、4. - ro 03-11-05 R. Monnin REV SHET REV SHET REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY RICK OFFICER DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY RAJESH PITHADIA COLUMBUS, OHIO 43216 http:/www.dscc.dla.m

3、il THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY RAYMOND MONNIN MICROCIRCUIT, DIGITAL-LINEAR, DUAL, 12-BIT, PROGRAMMABLE, DIGITAL-TO-ANALOG AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 99-12-17 CONVERTER WITH INTERNAL VOLTAGE REFERENCE, MONOLITHIC SILICON AMSC N

4、/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-99576 SHEET 1 OF 14 DSCC FORM 2233 APR 97 5962-E559-03 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRC

5、UIT DRAWING SIZE A 5962-99576 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device cl

6、ass V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 99576 01 Q P X Fe

7、deral stock class designator RHA designator (see 1.2.1) Devicetype (see 1.2.2) Device class designator Caseoutline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are ma

8、rked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as fol

9、lows: Device type Generic number Circuit function 01 TLV5638M Dual, 12-bit, programmable digital-to-analog converter with power down and internal reference. 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class

10、Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as desi

11、gnated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style P GDIP1-T8 or CDIP2-T8 8 Dual-in-line 2 CQCC1-N20 20 Square leadless chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appe

12、ndix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99576 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ra

13、tings. 1/ Supply voltage (VDDto AGND) 7 V Digital input voltage range to AGND -0.3 V VDD+0.3 V Reference input voltage range to AGND -0.3 V VDD+0.3 V Power dissipation (PD): (TA 25C) Case P 1050 mW 2/ Case 2 1375 mW 3/ Junction temperature (TJ) +150C Storage temperature range. -65C to +150C Lead tem

14、perature 1.6 mm (1/16 inch) from case for 10 seconds 260C Thermal resistance, junction-to-case (JC) See MIL-STD-1835 1.4 Recommended operating conditions. Supply voltage (VDD): With VDD= 5 V . 4.5 V to 5.5 V With VDD= 3 V . 2.7 V to 3.3 V Power on reset (POR) 0.55 V to 2.0 V High level digital input

15、 voltage (VIH): With VDD= 2.7 V 2.0 V minimum With VDD= 5.5 V 2.4 V minimum Low level digital input voltage (VIL): With VDD2.7 V . 0.6 V maximum With VDD5.5 V . 0.8 V maximum Reference voltage (Vrefto REF terminal): With VDD= 5 V . AGND to VDD-1.5 4/ With VDD= 3 V AGND to VDD-1.5 4/ Load resistance

16、(RL) 2 k Load capacitance (CL) (device type 01) . 100 pF maximum Clock frequency (fCLK) (device type 01) 20 MHz Ambient operating temperature range (TA) -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks

17、 form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT

18、 OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ For case P, the derating fact

19、or above TA= +25C is 8.4 mW/C. 3/ For case 2, the derating factor above TA= +25C is 11.0 mW/C. 4/ Due to the x2 output buffer, a reference input voltage (VDD 0.4 V) / 2 causes clipping of the transfer function. The output buffer of the internal reference must be disabled, if an external reference in

20、 used. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99576 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883

21、 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Unless otherwise indicated, copies of the specification,

22、 standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes pr

23、ecedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein

24、or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level

25、B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The ca

26、se outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Block diagrams. The block diagrams shall be as specified on figure 2. 3.3 Electrical performance characteristics and postirradiation parameter limits. U

27、nless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups s

28、pecified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is no

29、t feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall b

30、e in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML” or “Q” as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. Provided by IHS

31、Not for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99576 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Cond

32、itions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Power supply section Power supply current IDDVDD= 5 V, internal reference all inputs = 0 V or VDD,Fast 1,2,3 01 7.0 mA DAC latch = 0X800, no load Slow 3.6 VDD= 3 V, internal reference all inputs = 0

33、V or VDD,Fast 6.3 DAC latch = 0X800, no load Slow 3.0 VDD= 5 V, external reference all inputs = 0 V or VDD,Fast 6.3 DAC latch = 0X800, no load Slow 3.0 VDD= 3 V, external reference all inputs = 0 V or VDD,Fast 5.7 DAC latch = 0X800, no load Slow 2.6 Reference input section Input voltage range VINREF

34、IN = 2.048 V 1,2,3 01 0 VDD1.5 V Digital inputs section High level digital input current IIHVIN= VDD1,2,3 01 1 A Low level digital input current IILVIN= 0 V 1,2,3 01 -1 A Outputs section Output voltage range VOUTRL= 10 k 1,2,3 01 0 VDD-0.4 V Output load regulation accuracy VOLRVO= 4.096 V, 2.048 V,

35、RL= 2 k 1,2,3 01 0.25 % full scale volts See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99576 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL C SHEET 6

36、DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Static DAC section Resolution RES 1,2,3 01 12 bits Integral nonlinearity 2/ INL End point adjusted 1,2

37、,3 01 6 LSB Differential nonlinearity 3/ DNL 1,2,3 01 1 LSB Zero scale error, 4/ EZS 1,2,3 01 24 mV offset error at zero scale Gain error EG 5/ 1,2,3 01 0.6 % of FS voltage Analog output dynamic section Output slew rate SR CL= 100 pF, RL= 10 k, Slow 4 01 1.0 V/s TA= +25C, VOUTfrom 10% to 90% Fast 7.

38、0 Signal to noise ratio SNR fS= 480 kSPS, fOUT= 1 kHz, CL= 100 pF, RL= 10 k 4,5,6 01 69 dB Signal to noise + distortion SINAD fS= 480 kSPS, fOUT= 1 kHz, CL= 100 pF, RL= 10 k 4,5,6 01 58 dB Total harmonic distortion THD fS= 480 kSPS, fOUT= 1 kHz, CL= 100 pF, RL= 10 k 4,5,6 01 -57 dB Spurious free dyn

39、amic range SFDR fS= 480 kSPS, fOUT= 1 kHz, CL= 100 pF, RL= 10 k 4,5,6 01 57 dB See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99576 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHI

40、O 43216-5000 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics Continued. Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Limits Unit Min Max Digital input timing section Setup time, CS low before first neg

41、ative SCLK edge tsu (CS-CK) See figure 3 9,10,11 01 10 ns Setup time, 16thnegative SCLK edge before CS rising edge tsu (C16-CS) See figure 3 9,10,11 01 10 ns SCLK pulse width high tWHSee figure 3 9,10,11 01 25 ns SCLK pulse width low tWLSee figure 3 9,10,11 01 25 ns Setup time, data ready before SCL

42、K falling edge tsu(D)See figure 3 9,10,11 01 10 ns Hold time, data held valid after SCLK falling edge th(D)See figure 3 9,10,11 01 5 ns 1/ Unless otherwise specified, VDD= 2.7 V to 5.5 V for device type 01. 2/ The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity er

43、ror, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full scale errors. 3/ The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measure and ideal 1 LSB amplitude change o

44、f any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 4/ Zero scale error is the deviation from zero voltage output when the digital input code is zero. 5/ Gain error is the deviation from the ideal out

45、put (2 Vref 1 LSB) with an output load of 10 k excluding the effects of the zero-error. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99576 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION

46、LEVEL C SHEET 8 DSCC FORM 2234 APR 97 Device type 01 Case outlines P 2 Terminal number Terminal symbol 1 DIN NC 2 SCLK DIN 3 CS NC 4 OUTPUT A NC 5 AGND SCLK 6 REF NC 7 OUTPUT B CS 8 VDDNC 9 - NC 10 - OUTPUT A 11 - NC 12 - AGND 13 - NC 14 - NC 15 - REF 16 - NC 17 - OUTPUT B 18 - NC 19 - NC 20 - VDDNC

47、 = No connection FIGURE 1. Terminal connections. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99576 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL C SHEET 9 DSCC FORM 2234 APR 97 C

48、ase outlines P and 2 Terminal symbol I / O / P Description AGND P Ground CS I Chip select. Digital input active low, used to enable/disable inputs. DIN I Digital serial data input OUTPUT A O DAC A analog output OUTPUT B O DAC B analog output REF I / O Analog reference voltage input / output SCLK I Digital serial clock input VDDP Positive power supply FIGURE 1. Terminal connections Continued. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,

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