ECA 5670000-1991 EIA Commercial Component Model Specification《EIA商业元件模式规范》.pdf

1、ANSIIEIA-5670000-1991 APPROVED: octom 7, iaai O O O O h 75,000 ohms) R Standard resistive (25oR175,000 ohms) F Forcing or strong resistive (&O ohms) C Capacitance with aModierforlevt1 of capacitance NSP Not specified or unknown Letters uscd for strengths wiU be upper case. IA-5670000 Page 12 1.3 TAB

2、LE OF LEVELS FOR USE W“ ANALOG FUNCTIONS: E 1 An integer number representing a voltage level An integer number representing a curent levei While either upper or lower case letters may be used to idenMied levels. the lower case i is shown to avoid confusion with a 1. 1.4 TABLE OF ADDITIONAL LffiIC ST

3、ATES, STRENGTHS AND CONDONS USED MAINLY FOR TEST PURPOSES AND TO PROVIDE COMPATIBILITY W“ WAVES AND mss: T TF TR INT D C UR DI Do Transition, Le. not a O or a 1. This is a special form of A failing waveform from plus to minus voltage levels. A rising wavefonn from minus to plus voltage levels. X. Th

4、is is a further breakdown of T This is a further breakdown of T. Any integer number used in an aigorithm to define relative strength (algorithm must be available in my simuiation run to resolve contentions between . models) Dont Care. A relevancy factor. Can. Arelevancyfactor uwed Relevance A Signai

5、 direction into a port. A Signal direction out of a pon Ds A Drive and Sense/Monitor direaion DU Adirexionthatisunspecified JEDECStandardNumk lOOimher&nesTF andTR. Either upper or lowercase may be used for these temis. 2. FACTORS RELATED TOTHE LOGIC STATE-STRENGTH VALUE SYSTEM STANDARD: One of the m

6、ajordiffeiences among simuiatos patains to the logic states, snnigths and kv& aocommodated Hence, those tenns identified in Sections 3.4.2 and this Appendix an inocndebtobeaii-encompassing. whilediereissome - versus Mat is comiEXEsnenm the guidelines useci hen are to -astate as being exclusively rei

7、ated to a logic conditiaii, M the absence of such a condition, wide smnghs n idcntied thmu their applicabiuty to formdas for resolving contentions among signais or nodes (once connected togeth#) far detemnnui * gfiMllogicvallles SincebsetsOftbestaresand. snaigthsazieallowed,modelseandardizaa onupons

8、pecificenumerationtype declarations and assoami * VHDLpackaga RefertotheBlanLDetailedSpei6cauonforspecic cI1IIlIIcrBtioll type declamions keyed to cach of the principal technologies used in the processing of Commcrnal components. among simulator developers over what is considue to be a state STDOEIA

9、 5b70000-ENGL 1771 323Vb00 058Lib87 Tbb EIA-5670000 Page 13 Both the basic subsets for behavioral models and extensions were coordinated with the Waveform and Vector Exchange Specification (WAVES) in order to provide an integration path. WAVES is responsible for establishing the Test Vector Language

10、 for the Tester Independent Support Software System (TISSS). Hence, the tables of extended terms are provided in order to communicate those additional states, smngths and levels that can be used in conjunction with the testing of circuits incorporating commercial component models and to idenhfy cena

11、in other tem (i.e. Levels) that wiii be needed for modeling such components as A-D and D-A converters. EI A-5670000 Page 14 DEFINITIONS OF TERMS AND ACRONYMS ANSI: Amencan National Standards Institute. Ceed (or Validated) VHDL Simulators: Those full lu16 compatible VHDL simuiatm that have been valid

12、ated in accordance with a DoD sanctioned vaiidarion suite. Commercial Elecatmic Component: An electronic component sold commerciaily, i.e. a non-ASIC. It may be either mitary quaiied or non-military quaii- ned. while the specification can be applied to aii “Off-theahelf inte- grated circuits, it is

13、most applicable to those for which sud design infomation is not normaiiy provided. CMOS: CPU DID: Em EIA: FIFO: Em JEDEC Level: LRM: mos: m: RAD: ROM Complementary Metai Oxide Semiconductor Central procesSor UNt. Data item Description. A description of data item requirements which is iisted in the D

14、D1423 Fom included in Department of Defense solicita- tions. AU DIDS use the standard DD Fom 1664 first page. Emiaer coupled Logic. Electtonic Industries Association. First in First Out. A form of register. Institute of Electrical and Electronic Engineen. Joint Election Device Engineering Council (a

15、n EM organization). A numerical quantity which together with units represents an electrical position, such as a voltage levei or a cunent level, Language Reference Manuai. Specifically, the IEEE Standard 1076-1987. N-channelMetaiOxideSemiconductor programmable Logic Device. The tem PLD includes PALs

16、 and other semiconductor devices that are programmable. Radiationasinradiationhardnessorrelaaveresistancetoradiation fmm aipha particles. ReadonlyMew. scaling Factor: Areai number used as amultipiieir to modify times for derating purposes. The Scaling Factor, which defaults to 1.0, is used in the Ti

17、ming Module to aiter times based upon speciai system design quire- men6 withoutchangngthetabulated times in the timing table that a under congudon ConmL It should be noted that the Timing Module has provisions for scaling times due to voltage and temperaam variations without making use of the separa

18、te Scaling Factor variable. EIA-5670000 Page 15 State: Strength: The logicai condition of a signai appearing at a node or port in a digitai circuit or system. The power or force attribute of a signai used to resolve contentions at nodes that are connected together, such as in a wired-Or or a wired-A

19、nd configuration. A Subset model refers to one that does not incorporate aU functions defned in the data sheet. Subset as applied to simuiators means that not a of the VHIIL language is implemented, or cenain VHDL constructs are missing in accordance with the Language Reference Manual. Test Bench: A

20、ll test requirements and test facilities other than the test vectors and the model itelf. TISSS: Tester independent Support Software System. Throughput Time: The time delay from input port to output pon. Subset: m Transistor-Transistor Logic Value: VHDL: Quality or wonh, generaly ddved from the comb

21、ination of states, strengths and attributes, which relate to usefuiness or desirabiiity. VHSIC Hardware Description Languw. This language is described in refmnd EEE Standard 10761987. VHSIC: Very High Speed Integrated circuits. WAVES. Waveform and Vector Exchange Specincation. . Standard or Generic

22、Specification Standard Prefix for all Numbers Sectional Specification Designator Blank Detail Specification Designator 3 STD-EIA 5b7000O-ENGL 1991 323ibUU 0584b90 550 = EIA STANDARD AND SPECIFICATION NUMBERING . STANDARD A document that establishes engineering and technical requirements for processe

23、s, procedures, practices and methods that have been decreed by authorQ or adopted by consensus. Standards may also be established for selection, application and design criteria for material. Standards and other documents not in the specification format use only the EIA basic numbering system as foll

24、ows: EIA-123 Original Standard EIA-123-1 Addendum to Original Standard EIA-123-A First Revision of original Standard incorporating all Addenda SPECIFICATION A document prepared specifically to facilitate procurement which clearly and accurately describes the essential technical requirements for purc

25、hased material. Procedures necessary to determine that the requirements for the purchased material covered by the specification have been met shall also be referenced or included. IA Specifications use the following system: Detail Specification Designator A - EIA 123oooO EIA 123AOOO EIA 123AAOO EIA

26、123AAAA EIA 123OOAA is a Generic Specification is a Sectional Specification is a Blank Detail Specification is a Detail Specification is a Detail Specification for which no Sectional or Blank Detail Specification was issued. NOTES: 1. Some older specifications may not have been converted to this numbering system. 2. See EP-11 “Guide for the Preparation of Specification Using IECQ-System Format,“ for more detail. STD-EIA 5b70000-ENGL 1771 3234b00 OSdLib7I I77 9 4