ECA EIA-198-3-10-2015 Multilayer (Monolithic) Unencapsulated Ceramic Dielectric Surface-Mount Low Induction Chip Capacitors and Multi-Terminal Low Induction Capacitors.pdf

1、 EIA STANDARD Multilayer (Monolithic), Unencapsulated, Ceramic Dielectric, Surface-Mount Low Inductance Chip Capacitors and Multi-Terminal Low Inductance Capacitors EIA-198-3-10 August 2015 Electronic Components Industry Association ANSI/EIA-198-3-10-2015 Approved: August 21, 2015 EIA-198-3-10 NOTIC

2、E EIA Engineering Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay th

3、e proper product for his particular need. Existence of such Standards and Publications shall not in any respect preclude any member or nonmember of ECIA from manufacturing or selling products not conforming to such Standards and Publications, nor shall the existence of such Standards and Publication

4、s preclude their voluntary use by those other than ECIA members, whether the standard is to be used either domestically or internationally. Standards and Publications are adopted by ECIA in accordance with the American National Standards Institute (ANSI) patent policy. By such action, ECIA does not

5、assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the Standard or Publication. This EIA Standard is considered to have International Standardization implication, but the International Electrotechnical Commission activity has not progressed to th

6、e point where a valid comparison between the EIA Standard and the IEC document can be made. This Standard does not purport to address all safety problems associated with its use or all applicable regulatory requirements. It is the responsibility of the user of this Standard to establish appropriate

7、safety and health practices and to determine the applicability of regulatory limitations before its use. (From Standards Proposal No. 5224, formulated under the cognizance of the ECIA P-2.1 Ceramic Dielectric Capacitors Subcommittee.) Published by Electronic Components Industry Association 2015 EIA

8、Standards C400 + (20 x C) 2Whichever is less 3Per EIA-198, Section II, Method 101: For C1000pF, 1kHz + 10% 4EIA-198, Section II, Method 201 (Life at Elevated Temperature) or Method 205 (Humidity-Steady State) EIA-198-3-10 Page 6 EIA STANDARD SPECIFICATION SHEET MULTILAYER (MONOLITHIC), UNENCAPSULATE

9、D, CERAMIC DIELECTRIC, SURFACE-MOUNT LOW INDUCTANCE CHIP CAPACITORS AND MULTI-TERMINAL LOW INDUCTANCE Table 1b: Characteristic and Requirements for Multilayer Chip Capacitors (Fixed) Class II TCC Code Temperature Range (C) Temperature Characteristic Rated Voltage(Vdc) Cap & DF Volt/Freq. (Vrms/Hz) I

10、nitial DF Initial IR2Gor-F Post Test3 DF shift Post Test3 Cap Shift Post Test3 IR2Gor -F X5R -55C to +85C +15% 100 See note 10.035 10 or 500 200% 15% 1 or 50 50 0.035 1 or 50 25 0.035 1 or 50 16 0.0510 or 100 1 or 10 10 0.10 1 or 10 6.3 0.15 1 or 10 4.0 0.15 1 or 10 Notes: 1Per EIA-198, Section II,

11、Method 101: C 10 F, 0.5 + 0.2 Vrms/120+24 Hz. 2Whichever is less 3EIA-198, Section II, Method 201 (Life at Elevated Temperature) or Method 205 (Humidity-Steady State) EIA-198-3-10 Page 7 EIA STANDARD SPECIFICATION SHEET MULTILAYER (MONOLITHIC), UNENCAPSULATED, CERAMIC DIELECTRIC, SURFACE-MOUNT LOW I

12、NDUCTANCE CHIP CAPACITORS AND MULTI-TERMINAL LOW INDUCTANCE Table 1c: Characteristic and Requirements for Multilayer Chip Capacitors (Fixed) Class II TCC Code Temperature Range (C) Temperature Characteristic Rated Voltage(Vdc) Cap & DF Volt/Freq. (Vrms/Hz) Initial DF Initial IR2Gor-F Post Test3 DF s

13、hift Post Test3 Cap Shift Post Test3 IR2Gor -F X7R -55C to +125C +15% 100 See note 10.035 10 or 500 200% 15% 1 or 50 50 0.035 1 or 50 25 0.035 1 or 50 16 0.0510 or 100 1 or 10 10 0.10 1 or 10 6.3 0.15 1 or 10 4.0 0.15 1 or 10 X7S -55C to +125C +22% 10 See note 10.10 10 or 500 200% 15% 1 or 10 6.3 0.

14、154.0 0.15 Notes: 1Per EIA-198, Section II, Method 101: C 10 F, 0.5 + 0.2 Vrms/120+24 Hz. 2Whichever is less 3EIA-198, Section II, Method 201 (Life at Elevated Temperature) or Method 205 (Humidity-Steady State) EIA-198-3-10 Page 8 EIA STANDARD SPECIFICATION SHEET MULTILAYER (MONOLITHIC), UNENCAPSULA

15、TED, CERAMIC DIELECTRIC, SURFACE-MOUNT LOW INDUCTANCE CHIP CAPACITORS AND MULTI-TERMINAL LOW INDUCTANCE Environmental and Performance Test Requirements: General: Testing and requirements comply with EIA 198, Section II, Test Methods. Thermal Shock: Per EIA 198, Section II, Method 202. Test Condition

16、 B-3 using 100 cycles from -55C to +125C. Solderability: Both terminations shall be simultaneously tested and evaluated per EIA 198, Section II, Method 301. Resistance to Soldering Heat: Both terminations are to be evaluated for leach resistance in accordance with EIA 198, Section II, Method 302, Pr

17、ocedure 1 and Test Conditions F through H, as applicable based on the desired termination classification. Each of the end terminations is to be evaluated after solder immersion. Each shall possess a minimum of 95% coverage on each surface area with no exposure of internal electrodes or underlying ce

18、ramic. The minimum termination bandwidth (BW) after test shall be as defined in Figure 1. Resistance to Solvents: For marked components, per EIA 198, Section II, Method 310. No deterioration in marking legibility is permitted. Temperature Coefficient/Characteristic: The requirements for capacitance

19、change with temperature are, as shown in, Table 1 a-d, and are tested per EIA 198, Section II, Method 105. Application of voltage during test is not required. Humidity, Steady State: The requirements for capacitance change, dissipation factor/Q, and insulation resistance are as shown in Table 1 a-d.

20、 Testing is per EIA 198, Section II, Method 206 using conditions of 90-95% RH, 40C, no voltage applied, for a duration of 21 days. Life at Elevated Ambient Temperature: The requirements for capacitance change, dissipation factor/Q, and insulation resistance are as shown in Table 1 a-d. Testing is pe

21、r EIA 198, Section II, Method 201, Condition C (1000 hrs.). The test temperature for C0G, X7R and X7S is 125C + 3C, and for X5R is 85C + 3C. ECIA Document Improvement Proposal If in the review or use of this document, a potential change is made evident for safety, health or technical reasons, please

22、 fill in the appropriate information below and mail or FAX to: Electronic Components Industry Association EIA Standards & Technology Department 2214 Rock Hill Rd., Suite 265 Herndon, VA 20170 FAX: (571-323-0245) Document No.: Document Title: Submitters Name: Telephone No.: FAX No.: e-mail: Address:

23、Urgency of Change: Immediate: At next revision: Problem Area: a. Clause Number and /or Drawing: b. Recommended Changes: c. Reason/Rationale for Recommendation: Additional Remarks: Signature: Date: FOR ECIA USE ONLY Responsible Committee: Chairman: Date comments forwarded to Committee Chairman: Electronic Components Industry Association 2214 Rock Hill Road, Suite 265 * Herndon, VA 20170 * tel 571-323-0294 * fax 571-323-0245 www.ecianow.org