ECA EIA-364-96A-2017 TP-96A Plated Through Hole Integrity Test Procedure for Electrical Connectors.pdf

1、 EIA STANDARD TP-96A Plated Through Hole Integrity Test Procedure for Electrical Connectors EIA-364-96A (Revision of EIA-364-96) June 2017 Electronic Components Industry Association EIA-364-96A ANSI/EIA-364-96A-2017 Approved: June 19, 2017 NOTICE EIA Engineering Standards and Publications are design

2、ed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence of

3、such Standards and Publications shall not in any respect preclude any member or nonmember of ECIA from manufacturing or selling products not conforming to such Standards and Publications, nor shall the existence of such Standards and Publications preclude their voluntary use by those other than ECIA

4、 members, whether the standard is to be used either domestically or internationally. Standards and Publications are adopted by ECIA in accordance with the American National Standards Institute (ANSI) patent policy. By such action, ECIA does not assume any liability to any patent owner, nor does it a

5、ssume any obligation whatever to parties adopting the Standard or Publication. This EIA standard is considered to have International Standardization implications, but the International Electrotechnical Commission activity has not progressed to the point where a valid comparison between the EIA stand

6、ard and the IEC document can be made. This Standard does not purport to address all safety problems associated with its use or all applicable regulatory requirements. It is the responsibility of the user of this Standard to establish appropriate safety and health practices and to determine the appli

7、cability of regulatory limitations before its use. (From Standards Proposal No. 5389, formulated under the cognizance of the CE-2.0 Committee on EIA National Connector and Sockets Standards.) Published by Electronic Components Industry Association 2017 EIA Standards see figure 1. 1.4.2 Longitudinal

8、section A section taken perpendicular to the surface of a printed circuit board; see figure 2. 1.4.3 Radial hole distortion The measurement of how far the outside edge of the plated through hole has been distorted from the original hole contour as a result of the compliant section insertion. The mea

9、surement is taken from the transverse cross-section; see figure 1. EIA-364-96A Page 2 1.4.4 Plated through hole wall damage Any damage such as cracked plating in the plated through hole. 1.4.5 Inner conductor layer damage Includes any stretching of the inner conductor layers due to movement of the m

10、etal in the plated though hole as a result of compliant section insertion. This movement of the plated through hole metal may cause the inner conductor layers to “stretch” and/or “crack”. The evaluation is taken from a longitudinal cross-section; see figure 2. 2 Test resources 2.1 Equipment 2.1.2 Lo

11、w speed cutting saw or equivalent 2.1.3 Polishing equipment 2.1.4 Microscope with applicable magnification capability, (approximately between 50 and 250 times), to measure or observe the requirements as specified. 2.1.5 Photographic capability if required. 2.2 Materials Material to mount the specime

12、ns as required. Typical materials are two-part metallurgical cold mount epoxy or a thermoset or thermoplastic material suitable for hot mounting. Cold mounting is the preferred method. 2.3 Fixtures No fixtures are required for this method. 3 Test specimen 3.1 Description 3.1.1 The specimen consists

13、of a compliant pin inserted into a PTH. The reference document should indicate if this method is to be performed on a pin inserted once into a PTH or when a third pin is inserted into the same PTH, (usually this is performed to demonstrate repairability). If this method is used when a third pin is i

14、nserted, the previous two pins should each be new pins. EIA-364-96A Page 3 3.1.2 The printed circuit board shall be of a given thickness, with finished and drilled hole size as specified. If not specified, the board shall be four layer equidistant throughout the thickness. The hole pattern annular r

15、ings shall be specified in the reference document. The two inner layers shall consist of parallel traces interconnecting all contacts in each row. The trace width shall be 0.010 inch (0.254 millimeter) and the trace thickness shall be 1/2 ounce (17 micrometers) copper, unless otherwise specified in

16、the referencing document. 3.2 Preparation 3.2.1 The reference document shall specify the insertion depth of the pin into the PTH. 3.2.2 The pins shall be inserted oriented as normal for their application. If not specified the measurements shall be taken after the third insertion. NOTE The printed ci

17、rcuit board shall be adequately supported during the insertion process to minimize any flexure of the printed circuit board. 3.2.3 Five specimens shall be sectioned transversely and five shall be sectioned longitudinally unless otherwise specified. 3.2.4 The specimens should be placed in the metallu

18、rgical mounting material. It may be possible to fit more than one specimen in the same mount. 3.2.5 The reference document shall specify where the measurements are to be performed, (e.g., at the mid-plane, near the top, or bottom sections of the printed circuit board, (unless otherwise specified in

19、the referencing document the measurement shall be taken 0.012 inch +0.008 / -0.004 inch ( 0.3 millimeters +0.2 / -0.1 millimeter) in from the insertion side of the board). 4 Test procedure 4.1 Radial hole distortion (transverse section) The allowable radial hole distortion (a) of the drilled hole co

20、ntour in the PTH shall have an average distortion not greater than 0.0015 inch (37.5 micrometers) (with an absolute maximum distortion not greater than 0.002 inch (50 micrometers), unless otherwise specified in the referencing document. When viewed at the maximum magnification of 75X the remaining p

21、lating (b) shall be seen to completely separate the contact from printed wiring board non conductive matrix, thus ensuring that the contact has not penetrated completely through the hole plating, see figure 1, unless otherwise specified in the referencing document. EIA-364-96A Page 4 4.2 Hole wall d

22、amage (longitudinal section) The maximum allowable distortion (c) of the connected pattern to the PTH shall be specified in the reference document. Neither the PTH nor the interconnection layer may have cracks; see figure 2. 5 Details to be specified The following details shall be specified in the r

23、eferencing document: 5.1 Number of specimens, if other than 10 5.2 Printed circuit board thickness and material 5.3 Finished hole diameter, tolerance 5.4 Composition of finish in hole; e.g. copper, tin-lead, etc 5.5 Drilled hole diameter and tolerance 5.6 The PTH criteria, if other than specified in

24、 4.1 5.7 Trace width and thickness, if other than specified in 3.1.2 5.8 Annular ring dimensions 5.9 Pin insertion depth 5.10 If the PTH measurements shall be performed after the first, third, or other pin insertion, and any other special requirements to perform the test 5.11 Allowable drilled hole

25、distortion (a), if other than specified in 4.1 5.12 Type of sections required; transverse, longitudinal, or both 5.13 Allowable internal layer stretch or distortion (c) 5.14 Other physical damage such as cracks, pad lifting, etc. that may be cause for rejection 5.15 Depth of transverse section, if o

26、ther than specified in 3.2.5 EIA-364-96A Page 5 6 Documentation Documentation shall contain the details specified in clause 5, with any exceptions, and the following: 6.1 Title of test 6.2 Description of specimen 6.3 Description of printed circuit board 6.4 Description of pin insertion method and eq

27、uipment/tools 6.5 If the first or third pin insertion was used. 6.6 Test equipment used, and date of last and next calibration 6.7 Values and observations 6.8 Name of operator and date of test EIA-364-96A Page 6 Figure 1 Radial hole distortion (transverse section) NOTE Inner conductor layer trace sh

28、all be a minimum of 0.010 inch (0.25 millimeter) wide connecting to plated through hole. Figure 2 Hole wall damage (longitudinal section) ECIA Document Improvement Proposal If in the review or use of this document, a potential change is made evident for safety, health or technical reasons, please fi

29、ll in the appropriate information below and mail or FAX to: Electronic Components Industry Association EIA Standards & Technology Department 2214 Rock Hill Rd., Suite 265 Herndon, VA 20170 FAX: (571-323-0245) Document No.: Document Title: Submitters Name: Telephone No.: FAX No.: e-mail: Address: Urg

30、ency of Change: Immediate: At next revision: Problem Area: a. Clause Number and /or Drawing: b. Recommended Changes: c.Reason/Rationale for Recomendation: Additional Remarks: Signature: Date: FOR ECIA USE ONLY Responsible Committee: Chairman: Date comments forwarded to Committee Chairman: Revision H

31、istory Revision letter Project number Publication date Additions, changes and deletions - SP-3801-A & 3801-A-1 November 2002 Initially publication- SP-5186 November 2002 Reaffirmed 2 December 2009A SP-5389 Revised measurement dimension and tolerance in paragraph 3.2.5 to conform to industry standards Revised paragraph 2.2, 5.7, 5.13 and 6.4 for clarityElectronic Components Industry Association 2214 Rock Hill Road, Suite 265 * Herndon, VA 20170 * tel 571-323-0294 * fax 571-323-0245 www.ecianow.org