ECA EIA-595-A-2009 VISUAL AND MECHANICAL INSPECTION MULTILAYER CERAMIC CHIP CAPACITORS《多层瓷片电容器的表观 机械检验》.pdf

1、 EIA STANDARD VISUAL AND MECHANICAL INSPECTION MULTILAYER CERAMIC CHIP CAPACITORS (Revision of EIA-595) EIA-595-A FEBRUARY 2009 ANSI/EIA 595-A-2009 Approved: February 10, 2009 EIA-595-A EIA Standards Electronic Components Association NOTICE EIA Engineering Standards and Publications are designed to

2、serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence of such S

3、tandards and Publications shall not in any respect preclude any member or nonmember of EIA from manufacturing or selling products not conforming to such Standards and Publications, nor shall the existence of such Standards and Publications preclude their voluntary use by those other than EIA members

4、, whether the standard is to be used either domestically or internationally. Standards and Publications are adopted by EIA in accordance with the American National Standards Institute (ANSI) patent policy. By such action, EIA does not assume any liability to any patent owner, nor does it assume any

5、obligation whatever to parties adopting the Standard or Publication. This EIA Standard is considered to have International Standardization implication, but the International Electrotechnical Commission activity has not progressed to the point where a valid comparison between the EIA Standard and the

6、 IEC document can be made. This Standard does not purport to address all safety problems associated with its use or all applicable regulatory requirements. It is the responsibility of the user of this Standard to establish appropriate safety and health practices and to determine the applicability of

7、 regulatory limitations before its use. (From Standards Proposal No. 5094 formulated under the cognizance of the P-2.1 Committee on Ceramic Capacitors) Published by: ELECTRONIC COMPONENTS ASSOCIATION 2009 EIA Standards and Technology Department 2500 Wilson Boulevard Suite 310 Arlington, VA 22201 PRI

8、CE: Please call: Global Engineering Documents, USA and Canada (1-800-854-7179) http:/ All rights reserved Printed in U.S.A. PLEASE ! DONT VIOLATE THE LAW! This document is copyrighted by the EIA and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited

9、number of copies through entering into a license agreement. For information, contact: Global Engineering Documents 15 Inverness Way East Englewood, CO 80112-5704 or call USA and Canada (1-800-854-7179), International (303-397-7956) i CONTENTS Page Foreword iii Clause 1 Scope 1 2 Ceramic surface insp

10、ection 1 2.1 Cracks 1 2.2 Chipped areas 1 2.3 Pinholes, holes, and voids in the ceramic body 2 2.4 Delamination 3 2.5 Blisters or foreign material 3 2.6 Warpage and protrusions 4 2.7 Marking 4 3 End metallization inspection 4 3.1 Pinholes and voids 4 3.2 Bandwidth 5 3.3 Stringers and smears 5 3.4 Ed

11、ge reduction 6 3.5 Lifting or peeling of terminations 6 3.6 Foreign material 7 3.7 Bumps and protrusions 7 4 Pretinned solder termination inspection 7 4.1 Solder coverage 7 4.2 Leaching 8 4.3 Oversize 8 5 Plated nickel/tin or nickel/solder inspection 8 5.1 Barrier thickness 8 5.2 Tin or solder thick

12、ness 8 5.3 Plating bloom 9 5.4 Tarnished end metallization 9 Figures 1 Cracks 1 2 Chipping (chipouts and chipins) 2 3 Pinholes 2 4 Delamination 3 5 Blisters and foreign material 3 6 Warpage 4 7 Marking 4 8 End metallization voids 5 9 Bandwidth 5 10 Stringers 6 11 Chipped termination edges 6 12 Lifte

13、d terminations 6 13 Foreign material 7 14 Solder coverage and leaching 7 15 Oversize due to excessive solder dip buildup 8 Foreword This specification was prepared under the cognizance of the P-2.1 Subcommittee on Ceramic Dielectric Capacitors of the Electronic Industries Alliances sector Electronic

14、 Components, Assemblies, Equipment general requirements applicable to silver palladium, plated barriers, and solder dipped terminations 3.1 Pinholes and voids The end surfaces of the chips shall be completely covered (see figure 8). The other metallized surface areas shall be also be completely cove

15、red with the exception that pinholes or voids less than or equal to 5% of each individual surface area are allowed. Voids or pinholes which allow electrode exposure are unacceptable. Pinhole voids in end metallization which expose electr odes and voids greater than 5% of the metallized area on anyin

16、dividual metallized surface.RejectSmall voids not exposing electr odes and not exceeding 5% of the metallized ar ea on any surface.AcceptFigure 8 End metallization voids EIA-595-A, Visual and Mechanical Inspection Multilayer Ceramic Chip Capacitors Page 5 3.2 Bandwidth Termination gaps must not redu

17、ce the end metallization bandwidth to less than the minimum limit (see figure 9). Additionally 90% of the length of the top and bottom surface termination bands must be within the minimum and maximum dimensional limits. The sides are not required to meet any minimum limit. Note: There is no requirem

18、ent for the sides.AcceptMore than 90% of the metallization width on the top or bottom surface is within the min / max bandwidth requirement. Max DimensionMin DimensionRejectLess than 90% of the metallizationwidth on the top or bottom surface is within the min / max requirement.Max DimensionMin Dimen

19、sionFigure 9. Bandwidth 3.3 Stringers or smears End metallization stringers or smears must not exceed 20% of the unmetallized surface length, as measured linearly along the edge (see figure 10). Less than 20% of the linear unmetallized surface length.AcceptOver 20% of the linear unmetallized surface

20、 length.RejectFigure10. Stringers EIA-595-A, Visual and Mechanical Inspection Multilayer Ceramic Chip Capacitors Page 6 3.4 Edge reduction Mounting area edges must not be reduced by more than 10% due to chipping or termination processes (see figure 11). Note that normal rounding of the corners to pr

21、omote silver adhesion is not a rejectable phenomenon. More than 10% of metallizededges reduced by chipping.RejectFigure 11. Chipped termination edges 3.5 Lifting or peeling of terminations There shall be no evidence of termination lifting on the chip (see figure 12). In the case of plated chips, the

22、re may be a slight and acceptable amount of overplate beyond the edge of the barrier material. Termination lifted fr om cer amic sur face.RejectFigure 12. Lifted terminations EIA-595-A, Visual and Mechanical Inspection Multilayer Ceramic Chip Capacitors Page 7 3.6 Foreign material Foreign material (

23、including grease or oil) on the end metallizations may interfere with bonding and is not acceptable (see figure 13). 3.6 Bumps and protrusions Any surface irregularities must not cause the chip to exceed the warpage requirements, nor to fall outside the limits on length, width, and thickness. In add

24、ition, they must not cause a bonding problem (see figure 13). Foreign material, both smears and bumps, that may interfere with bonding process.RejectFigure 13. Foreign material 4 Solder-dipped termination inspection; additional requirements beyond the general end metallization inspection requirement

25、s NOTE Solder dipping is an alternate end metallization option. 4.1 Solder coverage Must be smooth, clean, non-dewetted, and must cover 90% or more of the base metallization on each mounting surface independently (see figure 14). Dewetting or leaching of the metallization areas. No leaching is allow

26、ed, and dewetting must be less than 10% of the area of each metallized surface.Reject Figure 14. Solder coverage and leaching EIA-595-A, Visual and Mechanical Inspection Multilayer Ceramic Chip Capacitors Page 8 4.2 Leaching There shall be no evidence of leaching (see figure 14). Leaching, when pres

27、ent, is typically found on the corners. It is the removal of the solderable base material, due to dissolution in the molten solder. 4.3 Oversize Solder dipping (when used by the chip manufacturer) shall not increase the overall length, width, or thickness dimensions in excess of the overall limit (s

28、ee figure 15). Note: As a guide, and not a requirement, solder dipping terminations normally will add no more than 10% of the unsoldered maximum dimension, or 0.306 mm (0.012“), whichever is greater. Excessive solder buildup increases any dimension (L, W , or T) beyond the maximum allowable.RejectT

29、maxW maxL maxFigure 15. Over size due to excessive solder dip buildup 5 Plated nickel/plated tin and plated solder inspection; additional requirements beyond the general end metallization inspection requirements NOTE: Plating is an end metallization option. Although it is the most common termination

30、 treatment, other options are available. 5.1 Barrier thickness Barrier plating (most commonly nickel) thickness shall be 1.27 micrometers (50 microinches) minimum and 625 micrometers (250 microinches) maximum. 5.2 Tin or solder thickness Tin or solder plating thickness must be a minimum of 2.54 micr

31、ometers (100 microinches.) 5.3 Plating bloom Any metallic spot that appears on the unmetallized ceramic surface, and extends through the top or bottom ceramic surface cover layers and contacts the electrode is not acceptable. Any exposed electrode on the side surfaces may also plate, and is not acce

32、ptable. Such areas are in electrical contact with the inner electrodes, and may result in short circuit problems. 5.4 Tarnished end metallization Any discolored or uniformly darkened area on the end metallization may be evidence of tarnished and unsolderable barrier metal, and should be rejected. EI

33、A Document Improvement Proposal If in the review or use of this document, a potential change is made evident for safety, health or technical reasons, please fill in the appropriate information below and mail or FAX to: Electronic Components Association Standards and Technology Department 2500 Wilson

34、 Blvd. Suite 310 Arlington, VA 22201 FAX: (703-875-8908) Document No.: Document Title: Submitters Name: Telephone No.: FAX No.: E-mail: Address: Urgency of Change: Immediate: At next revision: Problem Area: a. Clause Number and /or Drawing: b. Recommended Changes: c. Reason/Rationale for Recommendation: Additional Remarks: Signature: Date: FOR EIA USE ONLY Responsible Committee: Chairman: Date comments forwarded to Committee Chairman: Electronic Components Association 2500 Wilson Boulevard, Suite 310 * Arlington, VA 22201 * tel 703-907-8021 * fax 703-875-8908 www.ecaus.org