ECA EIA-964-2016 Specification for QSFP+ 10 Gb s Pluggable Transceiver.pdf

1、 EIA SPECIFICATION Specification for QSFP+ 10 Gb/s Pluggable Transceiver EIA-964 (Was SFF-8436, Rev 4.8, dated October 31, 2013) December 2016 Electronic Components Industry Association EIA-964 ANSI/EIA-964-2016 Approved: December 2, 2016 NOTICE EIA Engineering Specifications and Publications are de

2、signed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence

3、 of such Specifications and Publications shall not in any respect preclude any member or nonmember of ECIA from manufacturing or selling products not conforming to such Specifications and Publications, nor shall the existence of such Specifications and Publications preclude their voluntary use by th

4、ose other than ECIA members, whether the standard is to be used either domestically or internationally. Specifications and Publications are adopted by ECIA in accordance with the American National Standards Institute (ANSI) patent policy. By such action, ECIA does not assume any liability to any pat

5、ent owner, nor does it assume any obligation whatever to parties adopting the Specification or Publication. This EIA specification is considered to have International Standardization implications, but the International Electrotechnical Commission activity has not progressed to the point where a vali

6、d comparison between the EIA standard and the IEC document can be made. This Specification does not purport to address all safety problems associated with its use or all applicable regulatory requirements. It is the responsibility of the user of this Specification to establish appropriate safety and

7、 health practices and to determine the applicability of regulatory limitations before its use. NOTE The users attention is called to the possibility that compliance with this standard may require use of an invention covered by patent rights. By publication of this standard, no position is taken with

8、 respect to the validity of any such claim(s) or of any patent rights in connection therewith. If a patent holder has filed a statement of willingness to grant a license under these rights on reasonable and nondiscriminatory terms and conditions to applicants desiring to obtain such a license, then

9、details may be obtained from the standards developer. Neither the standards developer nor ANSI is responsible for identifying patents for which a license may be required by an American National Standard or for conducting inquiries into the legal validity or scope of those patents that are brought to

10、 their attention. (From Standards Proposal No. 5331-A, formulated under the cognizance of the CE-2.0 Committee on EIA National Connector and Socket Standards, and previously published by the SFF Committee as SFF-8436.) Published by Electronic Components Industry Association 2016 EIA Standards & Tech

11、nology Department 2214 Rock Hill Road, Suite 265 Herndon, VA 20170 PLEASE ! DONT VIOLATE THE LAW! This document is copyrighted by the ECIA and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreeme

12、nt. For information, contact: IHS 15 Inverness Way East Englewood, CO 80112-5704 or call USA and Canada (1-877-413-5186), International (303-397-7956) (This page left blank) i CONTENTS Clause Page Foreword . vii Background . viii 1 Introduction 1 1.1 Scope 1 1.2 Description of clauses 1 2 Applicable

13、 documents 2 2.1 Industry documents 2 2.2 SFF Specifications . 2 2.3 Sources . 2 2.4 Conventions . 3 3 Content . 3 4 Electrical specification . 7 4.1 Electrical connector . 7 4.1.1 Low speed electrical hardware pins . 12 4.1.1.1 ModSelL 12 4.1.1.2 ResetL 12 4.1.1.3 LPMode 12 4.1.1.4 ModPrsL 13 4.1.1

14、.5 IntL . 14 4.1.2 Low speed electrical specification . 14 4.1.3 High speed electrical specification 15 4.1.3.1 Rx(n)(p/n) 15 4.1.3.2 Tx(n)(p/n) . 15 4.2 Power requirements . 16 4.2.1 Host board power supply filtering . 17 4.3 ESD 19 5 Mechanical and board definition . 19 5.1 Introduction 19 5.2 QSF

15、P+ datums and component alignment . 20 5.3 QSFP+ module mechanical package dimensions 22 5.3.1 Mating of QSFP+ module PCB to QSFP+ electrical connector 25 ii CONTENTS (continued) Clause Page 5.4 Host PCB layout 26 5.4.1 Insertion, extraction and retention forces for QSFP+ modules . 27 5.5 Color codi

16、ng and labeling of QSFP+ modules 28 5.6 Bezel for systems using QSFP+ modules 29 5.6.1 Bezel for the thru bezel cage assembly version . 29 5.6.2 Bezel for the behind the bezel cage assembly version . 31 5.7 QSFP+ electrical connector mechanical . 32 5.8 Individual QSFP+ cage assembly versions 34 5.8

17、.1 QSFP+ heat sink clip dimensions 36 5.8.2 QSFP+ heat sink dimensions . 37 5.8.3 Light pipes . 38 5.9 Dust / EMI cover 38 5.10 Optical interface . 39 6 Environmental and thermal 41 6.1 Thermal requirements 41 7 Management interface 41 7.1 Introduction 41 7.2 Timing specification 41 7.2.1 Introducti

18、on 41 7.2.2 Management interface timing specification . 42 7.2.3 Serial interface protocol . 43 7.2.3.1 Management timing parameters . 43 7.3 Memory interaction specifications . 44 7.3.1 Timing for soft control and status functions 45 7.4 Device addressing and operation . 47 7.5 Read/write functiona

19、lity . 49 7.5.1 QSFP+ memory address counter (Read AND Write operations) 49 7.5.2 Read operations 50 7.5.2.1 Current address read . 50 7.5.2.2 Random read . 51 7.5.2.3 Sequential read 52 7.5.2.4 Sequential read from random start address 53 7.5.3 Write operations . 54 7.5.3.1 BYTE write 54 7.5.3.2 Se

20、quential write . 55 7.5.3.3 Acknowledge polling . 56 iii CONTENTS (continued) Clause Page 7.6 QSFP+ memory map . 56 7.6.1 Lower memory map . 58 7.6.1.1 Status indicator bits 59 7.6.1.2 Interrupt flags . 60 7.6.1.3 Module monitors 65 7.6.1.4 Channel monitoring . 67 7.6.1.5 Control bytes 69 7.6.1.6 Mo

21、dule and channel masks 71 7.6.1.7 Rate select (Byte 87-88) . 73 7.6.1.8 Password entry and change 74 7.6.2 Upper memory map Page 00h 75 7.6.2.1 Identifier (Address 128) . 78 7.6.2.2 Extended Identifier (Address 129) . 79 7.6.2.3 Connector (Address 130) . 80 7.6.2.4 Specification compliance (Address

22、131-138) 80 7.6.2.5 Encoding (Address 139) 82 7.6.2.6 BR, nominal (Address 140) . 82 7.6.2.7 Extended RateSelect compliance (Address 141) . 83 7.6.2.8 Length (Standard SM Fiber)-km (Address 142) 83 7.6.2.9 Length (OM3) (Address 143) 83 7.6.2.10 Length (OM2) (Address 144) 83 7.6.2.11 Length (OM1) (Ad

23、dress 145) 84 7.6.2.12 Cable assembly length (copper or active cable) (Address 146) . 84 7.6.2.13 Device tech (Address 147) . 84 7.6.2.14 Vendor name (Address 148-163) . 85 7.6.2.15 Extended module codes (Address 164) 85 7.6.2.16 Vendor OUI (Address 165-167) 86 7.6.2.17 Vendor PN (Address 168-183) 8

24、6 7.6.2.18 Vendor Rev (Address 184-185) . 86 7.6.2.19 Wavelength (Address 186-187) . 86 7.6.2.20 Wavelength tolerance (Address 188-189) . 87 7.6.2.21 Max case temp (Address 190) 87 7.6.2.22 CC_BASE (Address 191) 87 7.6.2.23 Options (Address 192-195) 87 7.6.2.24 Vendor SN (Address 196-211) 89 7.6.2.2

25、5 Date Code (Address 212-219) . 89 7.6.2.26 Diagnostic monitoring type (Address 220) 90 7.6.2.27 Enhanced options (Address 221) . 91 7.6.2.28 CC_EXT (Address 223) . 91 7.6.2.29 Vendor specific (Address 224-255) . 91 iv CONTENTS (continued) Clause Page 7.6.3 Upper memory map (Page 01h) . 92 7.6.4 Use

26、r writable and vendor specific memory . 92 7.6.5 Upper memory (Page 03h) . 93 7.6.5.1 Module and channel thresholds . 93 7.6.5.2 Optional channel controls 95 7.6.5.3 Channel monitor masks 96 Figure Page 1 Application reference model . 6 2 QSFP+ module pad layout 7 3a Example QSFP+ host board schemat

27、ic for optical modules . 10 3b Example QSFP+ host board schematic for passive copper cables . 11 4 Recommended host board power supply filtering 17 5 Instantaneous and sustained peak currents for Vcc1, Vcc Tx or Vcc Rx . 18 6 QSFP+ pluggable and direct attach module rendering . 20 7 QSFP+ datum alig

28、nment, depth 22 8 Drawing of QSFP+ module 23 9 QSFP+ module tab drawings . 24 10 Pattern layout for QSFP+ printed circuit board 25 11 QSFP+ host PCB mechanical layout 26 12 QSFP+ host PCB mechanical layout, detail Z 27 13a Recommended bezel design for cages that extend into or thru bezel . 30 13b Re

29、commended bezel design for cages that extend up against the inside surface of the bezel . 31 14 QSFP+ module electrical connector illustration . 32 15 QSFP+ electrical connector specification . 33 16 Thru bezel (left side) and behind the bezel (right side) cage and optional heat sink designs (explod

30、ed view) 34 17 1-by-1 thru bezel cage design . 35 18 QSFP+ heat sink clip 36 19 QSFP+ heat sink . 37 20 Dust / EMI cover . 38 21a QSFP+ Optical receptacle and channel orientation for MPO connector 39 21b QSFP+ Optical receptacle and channel orientation for dual LC connector 39 21c QSFP+ MPO optical

31、patchcord 40 21d QSFP+ dual LC optical patchcord 40 22 QSFP+ timing diagram . 42 23 QSFP+ device address 49 v CONTENTS (continued) Figure Page 24 QSFP+ current address read operation . 50 25 QSFP+ random read 51 26 Sequential address read starting at QSFP+ current address 52 27 Sequential address re

32、ad starting with random QSFP+ read 53 28 QSFP+ write byte operation . 54 29 QSFP+ sequential write operation 55 30 QSFP+ memory map 57 Table Page 1 Multimode fiber applications 5 2 Single mode fiber applications 5 3 Pin function definition (see Figure 10 for pad dimensions) . 8 4 Power mode truth ta

33、ble . 13 5 Low speed control and sense signals 14 6 Power supply specification . 18 7 Power budget classification 19 8 Definition of datums . 21 9 Insertion, extraction and retention forces 28 10 Temperature range class of operation . 41 11 Management interface timing parameters . 43 12 QSFP+ memory

34、 specification . 44 13 Single byte writable memory block 44 14 Multiple byte writable memory block . 44 15 Timing for QSFP+ soft control and status functions 45 16 I/O Timing for squelch & disable . 47 17 Lower memory map (A0h) . 58 18 Status indicators (Page A0) . 59 19 Channel status interrupt fla

35、gs (Page A0) 61 20 Module monitor interrupt flags (Page A0) 62 21 Channel monitor interrupt flags (Page A0) . 63 22 Module monitoring values (Page A0) . 66 23 Channel monitoring values (Page A0) 68 24 Control bytes (Page A0) 69 25 IntL masking bits for module and channel status interrupts (Page A0)

36、71 26 Functionality of byte 87 and 88: xN rate select with extended rate selection (Page A0) . 73 27 Definition of application select (Bytes 89 to 92 and Bytes 94 to 97) (Page A0) 74 vi CONTENTS (continued) Table Page 28 Detailed description of control mode (Page A0) 74 29 Serial ID data fields (Pag

37、e 00) 75 30 Identifier values (Address 128) (Page 00) 78 31 Extended identifier values (Address 129) (Page 00) 79 32 Connector values (Address 130) (Page 00) 80 33 Specification compliance (Address 131-138) (Page 00) 80 34 Encoding values (Address 139) (Page 00) 82 35 Extended RateSelect compliance

38、tag assignment (Address 141) (Page 00) . 83 36 Description of device technology (Address 147) (Page 00) . 84 37 Transmitter technology (Address 147 bits 7-4) (Page 00) 85 38 Extended module code values (Address 164) (Page 00) 85 39 Option values (Address 192-195) (Page 00) . 88 40 Date codes (Addres

39、s 212-219) (Page 00) . 89 41 Diagnostic monitoring type (Address 220) (Page 00) 90 42 Enhanced options (byte 221) (Page 00) 91 43 Application select table (Page 01) 92 44 Application code structure 92 45 Upper memory map (Page 03h) 93 46 Module and channel thresholds (Page 03) 94 47 Vendor specific

40、and optional channel controls (Page 03) 95 48 Output amplitude control (address 238-239) (Page 03) 96 49 Channel monitor masks (Page 03) . 96 vii Foreword (This foreword is informative only and is not part of this specification.) This Specification is from EIA Standards Proposal No. 5331, formulated

41、 under the cognizance of EIA CE-2.0, Committee on Connector and Socket Standards. This project was conducted in liaison with the SFF Committee as representing the disk drive industry. Utilization of this Standard is intended to eliminate misunderstandings or confusion between a manufacturer and user

42、 with respect to product performance and testing requirements for this as well as other possible applications. The development work on this specification was done by the SFF Committee, an industry group. The membership of the committee since its formation in August 1990 has included a mix of compani

43、es which are leaders across the industry. viii Background Abstract: This specification defines the electrical (copper), the optical and the mechanical characteristics of the pluggable Quad SFP+ Module/direct attach cable plug and connector. This document provides a common specification for systems m

44、anufacturers, system integrators, and suppliers of drives. This specification is made available for public review, and written comments are solicited from readers. Comments received by the members will be considered for inclusion in future revisions of this specification. EIA-964 Page 1 Specificatio

45、n for QSFP+ 10 Gb/s Pluggable Transceiver (From EIA Standards Proposal No. 5331, formulated under the cognizance of the EIA CE-2.0 Committee on National Connector and Socket Standards, and previously published by the SFF Committee as SFF-8436.) 1. Introduction 1.1 Scope In an effort to broaden the a

46、pplications for storage devices, an ad hoc industry group of companies representing system integrators, peripheral suppliers, and component suppliers decided to address the issues involved. 1.2 Description of clauses Clause 1 contains the Scope and Purpose Clause 2 contains Referenced and Related St

47、andards and SFF Specifications Clause 3 begins the specification Clause 4 contains electrical specifications Clause 5 contains mechanical specifications and printed circuit board recommendations Clause 6 contains environmental and thermal considerations Clause 7 is a description of the management in

48、terface and management register contents. EIA-965 Page 2 2 Applicable documents The following documents form a part of this specification to the extent indicated herein. In the event of conflict between this specification and the referenced documents, this specification shall take precedence. 2.1 In

49、dustry documents The following interface standards and specifications are relevant to this Specification. GR-253-CORE IEEE Std 802.3 IEEE Std 802.3ba InfiniBand Architecture Specifications INCITS 404 FC-PI-2 (Fibre Channel Physical Interface -2) INCITS 460 FC-PI-3 (Fibre Channel Physical Interface -3) INCITS 450 FC-PI-4 Fibre Channel Physical Interface -4) INCITS 457 SAS - 2 (Serial Attached SCSI - 2) INCITS 478 SAS - 2.1 (Serial Attached SCSI - 2.1) INF - 8438 QSFP 4X