ECA IS-36-1987 Chip Capacitors Multi-Layer (Ceramic Dielectric)《多层片状电容器(陶瓷电介质)》.pdf

1、EIA IS-3b 87 m 3234600 0002301 2 m - EIA INTERIM STANDARD CHIP CAPACITORS, MULTI-LAYER (CERAMIC DIELECTRIC) IS-36 Engineering Department ELBCTRONIC INDUSTRIES ASSOCIATION i c EIA IS-36 7 3234600 0002302 4 S NOTICE EIA Engineki-ing Standards and Publications are designed to serve the public intwest t

2、hrough eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence of such Standards and Pub- lications

3、 shall not in any respect preclude any member or non-member of EIA from manufacturing or selling products not conforming to such Standards and Publications, nor shall the existence of such Standards and Publications preclude their voluntary use by those other than EIA members, whether the standard i

4、s to be used either domestically or internationally. Recommended Standards and Publications are adopted by EIA without regard to whether or not their adoption may involve patents on articles, materials, or processes. By such action, EIA does not assume any liability to any patent owner, nor does it

5、assume any obligation whatever to parties adopting the Recom- mended Standard or Publication. EIA INTERIM CTANDA EIA Interim Standards contain information deemed to be of technical value to the industry, and are published at the request of the originating Committee without necessarily following the

6、rigorous public review and resolution of comments which is a procedural part of the development of an EIA Recom- mended Standard. IA Interim Standards should be reviewed on an annual basis by the formulating Committee and a decision made on whether to proceed to develop an EIA Recommended Standard o

7、n this subject. EIA Interim standards must be cancelled by the Committee and removed from the EIA Standards Catalog before the end of their fifth year of existence. Pub I i shed by TRIE S AS SOC I AT ION 2001 Eye Street, N.W. Washington, DL. 20006 PRICE: $8.00 COPYRIGHT I987 ELECTRONIG TNDIJSTRIBS A

8、SSOCIATION Printed in U.S.A. EIA IS-36 87 m 3234b00 0002303 b W i- - STYLE - CC0805 CC1206 IS-36 Page 1 minimum requirement. EIA 1s-36 87 m 3234boo 00023os T m IS-36 Page 3 . , -. - CLASS 1: Terminations are a leach-resistaht -*mtallization system not usually affected by the soldering pro- cess. Dew

9、etting is potentially a greater prob- lem than metallization removal during soldering. leaching metallizations or bythe protection of leachable metallizations by the use ofbarrier layers (typically of nickel or copper). Solder bond composition is not appreciably affected by metals added to the solde

10、r by the chip termina- % .- These terminations axe constructed by either non- ., %- . .tion;. -. .-. .- A- CLASS 2 and basic thiclmess, partic- ularly. over edges. Lower numbered classification designations nay in general be substituted for higher numbers in soldering applications. Wliick classifica

11、tions are suitable for what soldering processes is a question beyond Che scope of this specification. Capacitance Values, Tolerances, and Voltages: (1) COG (NPO): Table II (2) X7R: Table III (3) Z5U: Table IV Marlcing: Table V Environmental Rcauiremcnts: (1) The temperature coefficient of capacitanc

12、e or character- istics as shown Fn Table I shall be as specifled in RS-1.98-C. (2) When humidity tested to RS-198-C-Method B-3, Condition C, capacitors shall meet the capacitance change, the Q (dissipation factor), and insulation resistance require- ment of Table I. . (3) When life tested per RS-198

13、-C-Method C-2, the units - shall meet the capacitance change, the Q (dissipation factor), and insulation resistance requirement of Table I. IS-36 Page 4 PART NUMBER DESIGNATION Part number will be made from Tables II, III, or IV in the following manner: Style CC0805 CC1206 cc1210 CC1812 CC1825 cc Ce

14、racitanca Tolerance* COG, EIA C = k 0.25pF D = k O.SpF X7R, Code F=fX G= whichever is greater . . EIA IS-36 87 m 3234600 0002307 3 m IS-36 Page 5 14.Q Classification 1.1 1.2 1.3 1.4 . 1. 5 1.6 Type Designation: The type designation shall be in the following form: CCXXL U2J 470 G Style Characteristic

15、 Capacitance To 1 er an ce 501 1 Vo1t:age Termination Classification (For Chip capacitors only) - Stvle: The style is identified by the two letter symbol “CC“ followed by a two, three or four digit number; the letters identify the item as an EIA RS-198 part and the number identliies the shape and di

16、mensions of the capacitors (see individual. Specification Sheets) L. Characteristic: The characteriaric is identified by a letter-digir-letter symbol in accordance with Table I for Class T ciieiectrics, and Table II for classes II, III and IV dielectric. For Class I dielectrics, the first leeter ide

17、ntifies the nomine1 temperacure coefficient, the digit idencifies the multiplier and the final letter idencifies the tolerance of the temperature coefficienc. cemperaiure coefficient is expressed in parts per n illion per “C (pp/C). For Clesses II, III and I0 the first letter identifies the lox temp

18、erature requirementj the digit identifies the high temperature requirement, and the lest letter idenrifies the maximum capacitance change. The Capacitance and Tolerance: are identified by 3 digics and e letter .symbol. The first and second digits identify the first and second significant figures of

19、the capacitance; the third digit identifies the multiplier end the letter identifies the capacieance tolerance. See Tables I and II and the individuai Specification Sheets. The capacitance and tolerance Volcage: The voltage is-;idenai-fied-by 3 digits. The first and second digits idenzify the first

20、and second significant figures of the voltage and. rtis third identifies the multiplier. See Tables I and I1 an0 .rhe individual Specification Sheecs. Terminaiion Classification (Chips Only): The termination classification is identified by e single digit. See the individual Chip Specification Sheets

21、 for the digit idencification. EIA IS-36 87 m 3234600 0002308 5 m ! IS-36 Page 6 1.7 Marking L 1.7 eachcapac.iror shall show: (a) Capacitance in pF or pF and tolerance in percent or by letcer designation per Table I or Table II. above 999 in VF. The capacitance shall be expressed in a 3 digit code.

22、The first two dig,its shall besthe significant .figures and che third shall be che decimal multiplier;. . or Through 999 will be identified in pF, Type designation in accordance with Sp,ecificacion Sheer and Table 1 or Table II. (b) Temperacure Coefficient in parts per million per degree Cencigrade

23、or lecter designation in adcordznce wich Table I, or temperature characceriscic per Table 1.1. Manufaccurcrs name or symbol, EIA Code number. (c) (d) Indicacor of inner elecrrode eerminal (tubular styies only), comprising an .easily discernible dot despression. or Innerelectrode terminal shall be. l

24、ocated to the left of marking parallel to body.of. capacitor, or above circumferen,tial marking. 1.7.1.2 Color Marking: See Detail Section for the specific style of capaciror desired. 1.8 Chip Devices: The capacitors caE be marked by a letcer - digit code. See the indiidual Chip Specification Sheet

25、for the derails. o a 8 EIA-36 Page 7 2.0 Examination and measurcments : Examinations and. measurements to be modc before ond after tho tcst, as applicable, sholl be os spcci f icd in the. individual specification. 2.1 Interno1 Examination: Internal examination of the part shall be made- after the te

26、st to check for solder reflow or heat damage. 2.2 Termination Examination (chips only): Each of the. two chip end terminations ore to be considered separately after the Specified immersion cime. Each end termination area shall possess a minimum of 95% coverage on each surface area, with no exposed l

27、ectrodes or ceramic. On chips cith metallization on surfaces. other than Che ends, the minimum bsndvidth after immersion shall be 0.2rnm(8). Similorl*. the solder covered area shall not display lack of solcier coazirig for more than 5% of the area on any one surface. In cases of morginal performance

28、 to specification requirements, the initial andspost immersion solder costed areas will be characterized by acrual recorded dimensional measurements and the reduction Ca lculaced. 3.0 Summary: lnc iolloving details are to be specified in the individual specification: Tne use of heat sinks or shieldi

29、ng is prohibited, except rzhen they are part of the component (see 2.2). Solder terrninaLions that are not to be rested, if applicable (see 4). Special preparation of specime.ns if applicable (sec 4.1.1). Immersion of cerminations in. fiu, if.applicable (see 4.2). Depth oi immersion in the molten so

30、lder (see 4.4). lest condicion letter (see 4.4). Cooling time prior to final examinations ad measurements (see 4.4). Exminations and measuremencs before and after .test, are applicable (see 5). Illethod of internal inspecxior: shall be as specified (sec sal:. 4 EIA IS-36 7 3234b00 00023l.10 r O dP0

31、FIO .o O4 Li Ya dpm mru O0 +1+1 Oa ou u0 In knm ln4 I+ c 2 s Z u d dp m dp m dP O CiI +I ou U0 m Inru In4 I+ 12 x L k om E ES so O O0 44 dP 0 o O WU OUl da3 + O 3 kn N k a, u a a, % VI 4 & Q) a, c u 4 c 3 4 - EIA IS-3b 87 9 3234600 0002311 5 W Style cc0805 CC1206 cc1210 CC1812 CC1825 15-36 Page 9 TA

32、BLE Ii CHARACTERISTIC COG (NPO) Capacitanc Range Available Capacitance SOVdC Tolerance* 1OOVdc 1pF to 470pF 1pF CO 680pF 1pF CO 1000pF 11OOpF CO 2200pF 1800pF to 3300pF C, D, F, G, J, K 1pF to 1SOOpF 2400pF to 4700pF 3600pF to 0.OlQiiF 51OOpF to 6800pF 0.OllyF to 0.015tiF * Tightesr. tolerance avail

33、able is f 1% or -f. 0.25pF, whichever is greater EIA IS-36 87 3234600 0002332 7 IS-36 Page 10 TABLE III CHARACTERISTIC X7R Capacitance.Range Available Capacitance Stvle 3 OOVdc SOVdc To lerance - 220pF to 0.022vF 220pF to 0.047vF 0.056uF Co O.lvF 0.012vF to 0.22uF 0.27irF to 0.47uF CC0805 220pF to 3

34、900pF CC1206 22OpF to O.01SuF cc1210 0.022pF to 0.027uF CC1612 0.033pF to 0.056vF CC1625 0.068uF to 0.15vF K, N a - EIA IS-36 87 W 3234600 0002333 9 W IS - 36 Page 11 TABLE IV CHARACTERISTIC ZSU Capacitance Range Ava i 1 ab 1 e Capacitan ce 5OVdc Tolerance - Stvle .100Vdc - CC0805 470bpF to 0.022yF

35、CC1206 4700pF to 0.047vF cc1230 O.068uF to 0.10vF CC1812 0.15yF to 0.221iF CC1825 0.33uF to 0.471iF 4700pF to 0.047uF 4700pF to 0.10yF O.1SuF to 0.22yF 0.33pF to 0.47yF 0.68uF to 1.01.iF Z EIA IS-3b 87 m 3234b00 0002334 O m IS-36 Page 12 Capacitor Marking Alphabetic Significant Character Figures A 1

36、.0 B 1.1 C 1.2 D 1.3 E 1.5 F G H J K 1.6 1.8 2. o 2.2 2.4 L M N P Q 2.7 3. O 3.3 3.6 3.9 R S T U V. 4.3 4.7 5.1 5.6 6.2 w X Y Z 6.8 7.5 8.2 9.1 a b d f m n t Y e 2.5 3.5 4.0 4.5 5.0 6. O 7. O 8. O 9.0 Numeric Decimal Character Mu 1 t ip 1 ie r 5 6 7 8 9 10 o 10 102 103 10 y 105- 10 10 108 lo- Met ho

37、d of Marking: 1. The capacitance value is expressed in pF. 2. A two character marking system will be used. The first character will be an alphabetic symbol and it will designate the 1st and 2nd significant figures of capacitance. The second character will be a numerical digit and it will designate t

38、he decimal multipl.ier of capacitance. 3. The marking shall appear in black or legible con- trast. The size and orientation of the.marking shall be at the option of the supplier. / EXAMPLES: Al = 1 x 10 = 10pF r t J5 = 2.2 x 1.0 = 0.22 : 10 = 0.22uF IS-36 Page 13 TABLE VI RESISTANCE TO SOLQERING HEA

39、T (Supplements Table I, Page 46 of Hs-198-C for fiis.Tect) Immersion snd Conditior? Procedure Temperacure Duration Enersion Rete Test Immersion A 1 350 5 10C 3 4 0.5 seconds 25 k 6m/second (662 I18F) -0 seconds B 1 260 f SOC 10 i- 1 seconds 25 2 6m/second (500 rC 9.OF) C 7 260 -C 5C 10 2 2 seconds (

40、500 f 9F) D 2 260 f 5OC 20 f 2 seconds (500 5 9OF) E 2 280 f 5C 30 f 2 seconds (536 f 9F) FZ 1 260 f SOC 60 -i- 5 sec0nd.s 25 -+ 6mm/sacond (500 -I- 9F) G I 260 f SOC 30 f 3 seconds 25 5 6mm/second (SOO f 9F) H 1 260 5 5C 10 f 1 seconds 25 4 m/second (500 f 9F) rFr leaded specimens mounte2 on board

41、material, test . condition E is preferred. For chip devices, cest condition F is preferred. The tesF condition letter shall be as specified in the individual specification. and stabilize at room ambient conditions for the time noted in the individual specification before final examinations and measurments are made. After the dip the s.pecimens shall be allowed to cool