EN 16603-50-14-2014 en Space engineering - Spacecraft discrete interfaces《航天工程 航天器分散接口》.pdf

1、BSI Standards PublicationBS EN 16603-50-14:2014Space engineering Spacecraft discrete interfacesBS EN 16603-50-14:2014 BRITISH STANDARDNational forewordThis British Standard is the UK implementation ofEN 16603-50-14:2014.The UK participation in its preparation was entrusted to Technical Committee ACE

2、/68, Space systems and operations.A list of organizations represented on this committee can be obtained on request to its secretary.This publication does not purport to include all the necessary provisions of a contract. Users are responsible for its correct application. The British Standards Instit

3、ution 2014.Published by BSI Standards Limited 2014ISBN 978 0 580 84191 0 ICS 49.140 Compliance with a British Standard cannot confer immunity from legal obligations.This British Standard was published under the authority of the Standards Policy and Strategy Committee on 30 September 2014.Amendments/

4、corrigenda issued since publicationDate T e x t a f f e c t e dEUROPEAN STANDARD NORME EUROPENNE EUROPISCHE NORM EN 16603-50-14 September 2014 ICS 49.140 English version Space engineering - Spacecraft discrete interfaces Ingnierie spatiale - Interfaces lectriques discrtes pour satellites Raumfahrtte

5、chnik - Diskrete Schnittstellen in Raumfahrzeugen This European Standard was approved by CEN on 1 March 2014. CEN and CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard witho

6、ut any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC Management Centre or to any CEN and CENELEC member. This European Standard exists in three official versions (English, French, German). A version in

7、 any other language made by translation under the responsibility of a CEN and CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the same status as the official versions. CEN and CENELEC members are the national standards bodies and national electrotechnical c

8、ommittees of Austria, Belgium, Bulgaria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slove

9、nia, Spain, Sweden, Switzerland, Turkey and United Kingdom. CEN-CENELEC Management Centre: Avenue Marnix 17, B-1000 Brussels 2014 CEN/CENELEC All rights of exploitation in any form and by any means reserved worldwide for CEN national Members and for CENELEC Members. Ref. No. EN 16603-50-14:2014 EBS

10、EN 16603-50-14:2014Table of contents Foreword 6 1 Scope . 7 2 Normative references . 8 3 Terms, definitions and abbreviated terms 9 3.1 Terms from other standards 9 3.2 Terms specific to the present standard . 9 3.3 Abbreviated terms. 10 3.4 Conventions 11 3.4.1 Bit numbering convention 11 3.4.2 Tim

11、ing diagram conventions . 11 3.4.3 Signal and signal event naming convention 12 3.4.4 Signal timing and measurement references 13 4 General 14 4.1 Introduction . 14 4.2 Architectural concepts 14 4.2.1 Overview . 14 4.2.2 General failure tolerance . 15 4.2.3 Interface control during power cycling . 1

12、6 4.2.4 Cross-strapping . 17 4.2.5 Harness cross-strapping . 18 4.2.6 Cable capacitance. 21 5 Analogue signal interfaces 22 5.1 Overview 22 5.2 Analogue signal monitor (ASM) interface 22 5.2.1 General . 22 5.2.2 Analogue signal monitor interface . 24 5.3 Temperature sensors monitor (TSM) interface 2

13、6 5.3.1 Overview . 26 5.3.2 TSM acquisition layout 27 5.3.3 TSM acquisition resolution 27 5.3.4 TSM wire configuration . 27 EN 16603-50-14:2014BS EN 16603-50-14:20145.3.5 TSM electrical characteristics 28 6 Bi-level discrete input interfaces 36 6.1 Bi-level discrete monitor (BDM) interface 36 6.1.1

14、Overview . 36 6.1.2 Bi-level discrete monitor interface . 36 6.2 Bi-level switch monitor (BSM) interface . 38 6.2.1 General principles . 38 6.2.2 Bi-level switch monitor interface 39 7 Pulsed command interfaces 41 7.1 High power command (HPC) interfaces 41 7.1.1 General principles . 41 7.1.2 High po

15、wer command interface . 41 7.1.3 Low voltage high power command (LV-HPC) electrical characteristics . 42 7.1.4 High voltage high power command (HV-HPC) electrical characteristics . 44 7.1.5 High current high power command (HC-HPC) electrical characteristics . 45 7.1.6 Wiring type 46 7.1.7 High power

16、 command interface arrangement 46 7.2 Low power command (LPC) interface . 47 7.2.1 General . 47 7.2.2 Low power command interface . 47 7.2.3 LPC electrical characteristics 48 7.2.4 Wiring type 49 7.2.5 Interface arrangement . 49 8 Serial digital interfaces 50 8.1 Foreword 50 8.2 General principles o

17、f serial digital interfaces . 50 8.2.1 Overview . 50 8.2.2 General requirements . 51 8.3 16-bit input serial digital (ISD) interface 52 8.3.1 16-bit input serial digital interface description 52 8.3.2 Signals skew . 52 8.3.3 ISD interface timing specification 52 8.3.4 16-bit input serial digital int

18、erface: signal description . 55 8.4 16-bit output serial digital (OSD) interface description 57 8.4.1 16-bit output serial digital interface description 57 EN 16603-50-14:2014BS EN 16603-50-14:20148.4.2 Signals skew . 57 8.4.3 OSD interface timing specification . 58 8.4.4 16-bit output serial digita

19、l interface signal description 59 8.5 16-bit bi-directional serial digital (BSD) interface description . 61 8.6 Serial digital interface electrical circuits description . 62 8.7 Balanced differential serial digital interface signals . 63 8.7.1 Balanced differential serial digital interface - GATE_WR

20、ITE circuits . 63 8.7.2 Balanced differential serial digital interface - DATA_CLK_OUT circuits . 63 8.7.3 Balanced differential serial digital interface - DATA_OUT circuits 63 8.7.4 Balanced differential serial digital interface - DATA_IN circuits . 64 8.7.5 Balanced differential serial digital inte

21、rface - GATE_READ circuits . 64 8.8 Serial digital interface circuit electrical characteristics . 64 8.8.1 Introduction . 64 8.8.2 Provisions . 64 Annex A (informative) Tailoring guidelines . 68 Bibliography . 69 Figures Figure 3-1: Bit numbering convention . 11 Figure 3-2: Timing diagram convention

22、s . 12 Figure 3-3: Signal timing and measurement references 13 Figure 4-1: Architectural context of interfaces defined in this standard . 15 Figure 4-2: General scheme of redundant units cross-strapping 17 Figure 4-3: Example scheme for Single source Dual receiver cross-strapping 19 Figure 4-4: Exam

23、ple scheme for Dual source Single receiver cross-strapping 20 Figure 4-5: Cable capacitance definitions . 21 Figure 5-1: Analogue signal monitor (single ended source) interface arrangement 26 Figure 5-2: Analogue signal monitor (differential source) interface arrangement . 26 Figure 5-3: TSM1 refere

24、nce model . 29 Figure 5-4: Requirement for Rth/Rthas a function of RNORMand Rth. x = 0,01 . 29 Figure 5-5: TSM1 interface arrangement 31 Figure 5-6: TSM2 interface arrangement 33 Figure 5-7: Example TSM1 and 4K3A354 thermistor 34 Figure 5-8: Example TSM1 and YSI44907 thermistor . 34 Figure 5-9: Exam

25、ple TSM2 and PT1000 thermistor 35 Figure 6-1: BDM Interface configuration . 38 EN 16603-50-14:2014BS EN 16603-50-14:2014Figure 6-2: Switch status circuit interface arrangement 40 Figure 7-1: HPC interface arrangement 46 Figure 7-2: LPC active signal output voltage vs. load current . 48 Figure 7-3: L

26、PC-P and LPC-S interface arrangement . 49 Figure 8-1: 16-bit input serial digital (ISD) interface signal arrangement . 52 Figure 8-2: 16-bit input serial digital (ISD) interface 53 Figure 8-3: 16-bit output serial digital (OSD) interface signal arrangement . 57 Figure 8-4: 16-bit output serial digit

27、al (OSD) interface 58 Figure 8-5: 16-bit bi-directional serial digital interface signal arrangement 62 Figure 8-6: Balanced differential circuits for serial digital interfaces 63 Figure 8-7: Example of serial digital interface arrangement 65 Figure 8-8: Threshold levels for ECSS-E-50-14 differential

28、 circuits 67 Tables Table 5-1: Analogue signal monitor source circuit characteristics . 24 Table 5-2 Analogue signal receiver circuit characteristics . 25 Table 5-3: TSM1 source circuit characteristics . 29 Table 5-4: TSM1 receiver circuit characteristics . 30 Table 5-5: TSM2 source characteristics

29、. 32 Table 5-6: TSM2 receiver characteristics . 32 Table 6-1: BDM source characteristics . 37 Table 6-2: BDM receiver characteristics . 37 Table 6-3: Switch source characteristics 39 Table 6-4: Switch receiver characteristics. 40 Table 7-1: LV-HPC source characteristics 43 Table 7-2: LV-HPC receiver

30、 characteristics 43 Table 7-3: HV-HPC source characteristics . 44 Table 7-4: HV-HPC receiver characteristics . 45 Table 7-5: HC-HPC source characteristics . 45 Table 7-6: HC-HPC receiver characteristics . 46 Table 7-7: LPC source characteristics 48 Table 7-8: LPC receiver characteristics 49 Table 8-

31、1: 16-bit input serial digital (ISD) interface characteristics 54 Table 8-2: tbvalues. 56 Table 8-3: 16-bit output serial digital (OSD) interface characteristics 59 Table 8-4: Serial digital interface electrical characteristics 66 EN 16603-50-14:2014BS EN 16603-50-14:2014Foreword This document (EN 1

32、6603-50-14:2014) has been prepared by Technical Committee CEN/CLC/TC 5 “Space”, the secretariat of which is held by DIN. This standard (EN 16603-50-14:2014) originates from ECSS-E-ST-50-14C. This European Standard shall be given the status of a national standard, either by publication of an identica

33、l text or by endorsement, at the latest by March 2015, and conflicting national standards shall be withdrawn at the latest by March 2015. Attention is drawn to the possibility that some of the elements of this document may be the subject of patent rights. CEN and/or CENELEC shall not be held respons

34、ible for identifying any or all such patent rights. This document has been prepared under a mandate given to CEN by the European Commission and the European Free Trade Association. This document has been developed to cover specifically space systems and has therefore precedence over any EN covering

35、the same scope but with a wider domain of applicability (e.g. : aerospace). According to the CEN-CENELEC Internal Regulations, the national standards organizations of the following countries are bound to implement this European Standard: Austria, Belgium, Bulgaria, Croatia, Cyprus, Czech Republic, D

36、enmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and the United Kingdom. EN 16603-50

37、-14:2014BS EN 16603-50-14:20141 Scope This standard specifies a common set of spacecraft onboard electrical interfaces for sensor acquisition and actuator control. The interfaces specified in this standard are the traditional point-to-point interfaces that are commonly used on modern spacecraft. The

38、 interfaces specified in this standard include analogue and discrete digital interfaces used for status measurement and control, as well as point-to-point serial digital interfaces used for digital data acquisition and commanding of devices. This standard specifies: interface signal identification;

39、interface signal waveforms; signal timing requirements; signal modulation; voltage levels; input and output impedance; overvoltage protection requirements; bit ordering in digital data words; cabling requirements where appropriate. This standard does not cover: connector requirements; digital data w

40、ord semantics; message or block formats and semantics. Connector requirements are not covered because these are normally mission or project specific. The goal of this standard is to establish a single set of definitions for these interfaces and to promote generic implementations that can be re-used

41、throughout different missions. When referred, the present standard is applicable as a complement of the already existing interface standards ANSI/TIA/EIA-422B-1994 and ITU-T Recommendation V.11 (Previously “CCITT Recommendation”) (03/93). Guidance for tailoring of the present standard can be found i

42、n Annex A. This Standard may be tailored for the specific characteristics and constraints of a space project in conformance with ECSS-S-ST-00. EN 16603-50-14:2014BS EN 16603-50-14:20142 Normative references The following normative documents contain provisions which, through reference in this text, c

43、onstitute provisions of this ECSS Standard. For dated references, subsequent amendments to, or revisions of any of these publications, do not apply. However, parties to agreements based on this ECSS Standard are encouraged to investigate the possibility of applying the most recent editions of the no

44、rmative documents indicated below. For undated references the latest edition of the publication referred to applies. EN reference Reference in text Title EN 16601-00-01 ECSS-S-ST-00-01 ECSS system - Glossary of terms ANSI/TIA/EIA-422B-1994 Electrical characteristics of balanced voltage digital inter

45、face circuits ITU-T Recommendation V.11 (Previously “CCITT Recommendation”) (03/93) Electrical characteristics for balanced double-current interchange circuits operating at data signalling rates up to 10 Mbit/s NOTE This document is technically equivalent to ANSI/TIA/EIA/422B-1994. EN 16603-50-14:20

46、14BS EN 16603-50-14:20143 Terms, definitions and abbreviated terms 3.1 Terms from other standards For the purpose of this Standard, the terms and definitions from ECSS-ST-00-01 apply. 3.2 Terms specific to the present standard 3.2.1 accuracy closeness of a measurement to the actual quantity being me

47、asured NOTE For the purposes of this Standard it is expressed as percentage of the full measurement range or as an absolute value. 3.2.2 circuit conducting path which conveys a signal across the interface from the signal source to the signal destination NOTE A circuit includes the cable conductor, a

48、ny intervening connectors, and any circuit elements such as protection resistors and coupling capacitors, which make up the signal path. 3.2.3 DHS data interchange bus underlying communication medium which connects the DHS core elements NOTE This can consist of more than one physical bus. 3.2.4 DHS

49、core element component of a data handling system which has a direct connection to the DHS data interchange bus NOTE E.g.: bus controllers and remote terminals. 3.2.5 DHS peripheral element component of a data handling system which does not have a direct connection to the DHS data interchange bus NOTE E.g.: sensors and actuators. EN 16603-50-14:2014BS EN 16603-50-14:20143.2.6 ground displacement voltage voltage difference between source and receiver ground references NOTE Users are encouraged to use this definition instead of common mode voltage