EN 60191-6-17-2011 en Mechanical standardization of semiconductor devices - Part 6-17 General rules for the preparation of outline drawings of surface mounted semiconductor device .pdf

1、raising standards worldwideNO COPYING WITHOUT BSI PERMISSION EXCEPT AS PERMITTED BY COPYRIGHT LAWBSI Standards PublicationMechanical standardization of semiconductor devicesPart 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device packages Design guide

2、for stacked packages Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P PFLGA)BS EN 60191-6-17:2011National forewordThis British Standard is the UK implementation of EN 60191-6-17:2011. It isidentical to IEC 60191-6-17:2011.The UK participation in its preparation was entrusted

3、to Technical CommitteeEPL/47, Semiconductors.A list of organizations represented on this committee can be obtained onrequest to its secretary.This publication does not purport to include all the necessary provisions of acontract. Users are responsible for its correct application. BSI 2011 ISBN 978 0

4、 580 57621 8 ICS 01.100.25; 31.080.01Compliance with a British Standard cannot confer immunity from legal obligations.This British Standard was published under the authority of the Standards Policy and Strategy Committee on 30 June 2011.Amendments issued since publicationAmd. No. Date Text affectedB

5、RITISH STANDARDBS EN 60191-6-17:2011EUROPEAN STANDARD EN 60191-6-17 NORME EUROPENNE EUROPISCHE NORM April 2011 CENELEC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung Management Centre: Avenue Ma

6、rnix 17, B - 1000 Brussels 2011 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. No. EN 60191-6-17:2011 E ICS 31.080.01 English version Mechanical standardization of semiconductor devices - Part 6-17: General rules for the preparation of

7、outline drawings of surface mounted semiconductor device packages - Design guide for stacked packages - Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA) (IEC 60191-6-17:2011) Normalisation mcanique des dispositifs semiconducteurs - Partie 6-17: Rgles gnrales pour la pr

8、paration des dessins dencombrement des dispositifs semiconducteurs montage en surface - Guide de conception pour les botiers emplils - Botiers matriciels billes et pas fins et botiers matriciels zone de contact plate et pas fins (P-PFBGA et P-PFLGA) (CEI 60191-6-17:2011) Mechanische Normung von Halb

9、leiterbauelementen - Teil 6-17: Allgemeine Regeln fr die Erstellung von Gehusezeichnungen von SMD-Halbleitergehusen - Konstruktionsleitfaden fr gestapelte Gehuse - Feinraster-Ball-Grid-Array und Feinraster-Land-Grid-Array (P-PFBGA/P-PFLGA) (IEC 60191-6-17:2011) This European Standard was approved by

10、 CENELEC on 2011-03-03. CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national st

11、andards may be obtained on application to the Central Secretariat or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and n

12、otified to the Central Secretariat has the same status as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, the Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latv

13、ia, Lithuania, Luxembourg, Malta, the Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland and the United Kingdom. BS EN 60191-6-17:2010EN 60191-6-17:2011 - 2 - Foreword The text of document 47D/785/FDIS, future edition 1 of IEC 60191-6-17, prepared by SC 47

14、D, Mechanical standardization for semiconductor devices, of IEC TC 47, Semiconductor devices, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 60191-6-17 on 2011-03-03. Attention is drawn to the possibility that some of the elements of this document may be the subject

15、 of patent rights. CEN and CENELEC shall not be held responsible for identifying any or all such patent rights. The following dates were fixed: latest date by which the EN has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2011-12-03 late

16、st date by which the national standards conflicting with the EN have to be withdrawn (dow) 2014-03-03 Annex ZA has been added by CENELEC. _ Endorsement notice The text of the International Standard IEC 60191-6-17:2011 was approved by CENELEC as a European Standard without any modification. _ BS EN 6

17、0191-6-17:2011- 3 - EN 60191-6-17:2011 Annex ZA (normative) Normative references to international publications with their corresponding European publications The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applie

18、s. For undated references, the latest edition of the referenced document (including any amendments) applies. NOTE When an international publication has been modified by common modifications, indicated by (mod), the relevant EN/HD applies. Publication Year Title EN/HD Year IEC 60191-6 - Mechanical st

19、andardization of semiconductor devices - Part 6: General rules for the preparation of outline drawings of surface mounted semiconductor device packages EN 60191-6 - IEC 60191-6-5 - Mechanical standardization of semiconductor devices - Part 6-5: General rules for the preparation of outline drawings o

20、f surface mounted semiconductor device packages - Design guide for fine-pitch ball grid array (FBGA) EN 60191-6-5 - BS EN 60191-6-17:2011 2 60191-6-17 IEC:2011 CONTENTS INTRODUCTION . 5 1 Scope . 6 2 Normative references . 6 3 Definitions 6 4 Terminal position numbering 7 5 Drawings 8 6 Dimensions 1

21、6 6.1 Group 1 . 16 6.2 Group 2 . 21 7 Dimension table . 27 Figure 1 Individual stackable package, P-FBGA (cavity-up) . 8 Figure 2 Individual stackable package, P-FBGA (cavity-down) . 9 Figure 3 Individual stackable package, P-FLGA (cavity-up) . 10 Figure 4 Stacked package outline, P-PFBGA (cavity-up

22、 BGA and cavity-up BGA) . 11 Figure 5 Stacked package outline, P-PFBGA (cavity-down BGA and cavity-down BGA) 12 Figure 6 Stacked package outline, P-PFBGA (cavity-down BGA + cavity-up LGA） . 13 Figure 7 Stacked package outline, P-PFLGA (cavity-up LGA + cavity-up BGA) 14 Figure 8 Functional gauge . 15

23、 Figure 9 Pattern of terminal position area 15 Table 1 Dimensions, Group 1 . 16 Table 2 Dimensions Group 2 21 Table 3 Combination of D, E, MD, and ME, e = 0.80mm pitch FBGA and FLGA . 22 Table 4 Combination of D, E, MD, and ME, e = 0,65mm pitch FBGA and FLGA . 23 Table 5 Combination of D, E, MD, and

24、 ME, e = 0,50mm pitch FBGA and FLGA . 24 Table 6 Combination of D, E, MD, and ME, e = 0,40mm pitch FBGA an FLGA . 25 Table 7 Combination of D, E, MD, and ME, e = 0,30mm pitch FLGA. 26 Table 8 Dimension table 27 BS EN 60191-6-17:201160191-6-17 IEC:2011 5 INTRODUCTION The trend toward downsizing and h

25、igher density of portable electronic devices has driven LSI packages into smaller and higher density configurations. The market demand of higher density has led to the development of the package stacking technology that enabled miniaturization and higher functionality. The objective of this design g

26、uide is to standardize outlines and to get interchangeability of individual stackable packages. BS EN 60191-6-17:2011 6 60191-6-17 IEC:2011 MECHANICAL STANDARDIZATION OF SEMICONDUCTOR DEVICES Part 6-17: General rules for the preparation of outline drawings of surface mounted semiconductor device pac

27、kages Design guide for stacked packages Fine-pitch ball grid array and fine-pitch land grid array (P-PFBGA and P-PFLGA) 1 Scope This part of IEC 60191 provides outline drawings and dimensions for stacked packages and individual stackable packages in the form of FBGA or FLGA. 2 Normative references T

28、he following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced document applies. IEC 60191-6, Mechanical standardization of semiconductor devices Part 6: Gene

29、ral rules for the preparation of outline drawings of surface mounted semiconductor device package IEC 60191-6-5, Mechanical standardization of semiconductor devices Part 6-5: General rules for the preparation of outline drawings of surface mounted semiconductor device packages - Design guide for fin

30、e-pitch ball grid array (FBGA) 3 Terms and definitions For the purposes of this document, the terms and definitions given in IEC 60191-6 and the following apply. 3.1 individual stackable package package with an array of metallic balls or lands on the underside of the package for the purpose of surfa

31、ce-mount on a printed circuit board and an array of footprints (lands) on the upper side of the package for stacking packages NOTE The individual stackable cavity-up FLGA package is a part of this specification on the premise of stacking a cavity-down FBGA with cavity-up FLGA. 3.2 stacked package as

32、sembly of multiple individual stackable packages in a stacked configuration NOTE The top package can be a standard FBGA specified in IEC 60191-6-5 without any footprints on the upper side of the package. The stand-off height of this standard package, however, shall follow this design guide. 3.3 moul

33、d cap height (A2) height of the mould cap which contains wire-bonded die or of the exposed flip chip-bonded die with respect to the upper substrate surface of the package BS EN 60191-6-17:201160191-6-17 IEC:2011 7 3.4 distance between the mould cap edge and innermost balls (F) distance between the m

34、ould cap edge of the lower package and the innermost terminals of the upper package of the stacked package 3.5 upper side land grid pitch (e1) grid pitch of the footprints (lands) on the upper side of the individual stackable package. They will be interconnected with the terminals of a mating upper

35、package 3.6 parallelism tolerance of the mould cap surface (y1) parallelism tolerance of the top mould-cap surface of the stacked package or the individual stackable package with respect to the seating plane (datum S), which is established by contact of the crowns of the balls NOTE For the stacked p

36、ackage, “y1” is defined as the parallelism tolerance of the top-component surface with regard to the seating plane of the lowest component. 3.7 coplanarity (y) flatness tolerance controlling the lowest points of the terminals of the individual stackable package or the stacked package 3.8 diameter of

37、 the upper side lands (b2) diameter of the upper side lands, which will be bonded to the terminals of the mating upper package 4 Terminal position numbering When a package is viewed from the terminal side with the index corner in the bottom left corner position, terminal rows are lettered from botto

38、m to top starting with A, then B, C, AA, AB, etc., while terminal columns are numbered from left to right starting with 1. Terminal positions are designated by a row-column grid system and shown as alphanumeric identification, e.g., A1, B1, or AC34. The letters I, O, Q, S, X and Z are not used for n

39、aming the terminal rows. BS EN 60191-6-17:2011 8 60191-6-17 IEC:2011 5 Drawings Outline drawings are shown in Figure 1, 2, 3, 4, 5, 6 and 7. (1)(3)(4)(2)Be1EAe1D1 2 3 4ABCDn b2x1 M S A M B Mx2 MSA2A1Ay1 Sy CZSee1 2 3 4ABCD(3)(4)n bx1 M S A M B Mx2 MSTop viewSide viewBottom view IEC 164/11Figure 1 In

40、dividual stackable package, P-FBGA (cavity-up) BS EN 60191-6-17:201160191-6-17 IEC:2011 9 (1)(3)(4)(2)Be1EA e 1D 1 2 3 4A B C D n b2x1 M S A M B Mx2 MSA 2A 1A y1Sy CZ S e e 1 2 3 4ABCD(3)(4)n b x1 M S A M B Mx2 MSTop viewSide viewBottom viewIEC 165/11 Figure 2 Individual stackable package, P-FBGA (c

41、avity-down) BS EN 60191-6-17:2011 10 60191-6-17 IEC:2011 (1)(3)(4)(2)Be1EAe1D1 2 3 4ABCDn b2 x1 M S A M B Mx2 MSA2A1Ay1Sy CZSee1 2 3 4ABCD(3)(4)n b1 x1 M S A M B Mx2 MSTop viewSide viewBottom viewYYSection Y-YIEC 166/11Figure 3 Individual stackable package, P-FLGA (cavity-up) BS EN 60191-6-17:201160

42、191-6-17 IEC:2011 11 (1)(3)(4)(2)Be1EAe1D1 2 3 4ABCDn b2 x1 M S A M B Mx2 MSA2A1Ay1Sy CZSee1 2 3 4ABCD(3)(4)n b x1 M S A M B Mx2 MSTop viewSide viewBottom viewFIEC 167/11Figure 4 Stacked package outline, P-PFBGA (cavity-up BGA and cavity-up BGA) BS EN 60191-6-17:2011 12 60191-6-17 IEC:2011 (1)(3)(4)

43、(2)Be1EAe1D1 2 3 4ABCDn b2x1 M S A M B Mx2 MSA2A1Ay1 Sy CZSee1 2 3 4ABCD(3)(4)n bx1 M S A M B Mx2 MSTop viewSide viewBottom viewIEC 168/11Figure 5 Stacked package outline, P-PFBGA (cavity-down BGA and cavity-down BGA) BS EN 60191-6-17:201160191-6-17 IEC:2011 13 (1)(3)(4)(2)Be1EAe1D1 2 3 4ABCDn b2 x1

44、 M S A M B Mx2 MSA2A1Ay1 Sy CZSee1 2 3 4ABCD(3)(4)n bx1 M S A M B Mx2 MSTop viewSide viewBottom viewIEC 169/11Figure 6 Stacked package outline, P-PFBGA (cavity-down BGA + cavity-up LGA）BS EN 60191-6-17:2011 14 60191-6-17 IEC:2011 (1)(3)(4)(2)Be1EAe1D1 2 3 4ABCDn b2x1 M S A M B Mx2 MSA2A1Ay1 Sy CZSee

45、1 2 3 4ABCD(3)(4)n b1 x1 M S A M B Mx2 MSTop viewSide viewBottom viewYYFSection Y-YIEC 170/11Figure 7 Stacked package outline, P-PFLGA (cavity-up LGA + cavity-up BGA) BS EN 60191-6-17:201160191-6-17 IEC:2011 15 Common notes for Figure 1 to Figure 7. (1) The datum S is defined as the seating plane on

46、 which a package free stands by contact of the balls. (2) The hatched zone indicates the index-marking area where A1 terminal locates. The index-marking area is basically 1/16 of the package body area in compliance with IEC standard. Even if the index mark extends more than this area, it shall not e

47、xtend more than 1/4 of the package body area. (3) The terminal true position tolerances x1and x2are applied to all terminals. (4) The terminal diameter b, b1, and b2are the largest diameters as measured in a plane parallel to the seating plane. The functional gauge drawing indicates the pattern of t

48、he circles, in which terminals locate, with respect to the datum S, A, and B. The pattern of terminal position area is composed of the circles, in which terminals locate, with respect to the datum S. EmaxeeDmaxb3b4ee(5) (6)IEC 171/11 IEC 172/11Figure 8 Functional gauge Figure 9 Pattern of terminal p

49、osition area BS EN 60191-6-17:2011 16 60191-6-17 IEC:2011 6 Dimensions 6.1 Group 1 Dimensions of group 1 are shown in Table 1. Table 1 Dimensions, Group 1 Unit: mm Term Symbol Specification Recom- mended value Remarks Package nominal dimension E D A package nominal dimension is defined as “package width E length D”, wh