1、BRITISH STANDARDBS EN 62373:2006Bias-temperature stability test for metal-oxide, semiconductor, field-effect transistors (MOSFET)The European Standard EN 62373:2006 has the status of a British StandardICS 31.080g49g50g3g38g50g51g60g44g49g42g3g58g44g55g43g50g56g55g3g37g54g44g3g51g40g53g48g44g54g54g44
2、g50g49g3g40g59g38g40g51g55g3g36g54g3g51g40g53g48g44g55g55g40g39g3g37g60g3g38g50g51g60g53g44g42g43g55g3g47g36g58BS EN 62373:2006This British Standard was published under the authority of the Standards Policy and Strategy Committee on 29 September 2006 BSI 2006ISBN 0 580 49255 9National forewordThis B
3、ritish Standard was published by BSI. It is the UK implementation of EN 62373:2006. It is identical with IEC 62373:2006.The UK participation in its preparation was entrusted to Technical Committee EPL/47, Semiconductors.A list of organizations represented on EPL/47 can be obtained on request to its
4、secretary.This publication does not purport to include all the necessary provisions of a contract. Users are responsible for its correct application.Compliance with a British Standard cannot confer immunity from legal obligations. Amendments issued since publicationAmd. No. Date CommentsEUROPEAN STA
5、NDARD EN 62373 NORME EUROPENNE EUROPISCHE NORM August 2006 CENELEC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europisches Komitee fr Elektrotechnische Normung Central Secretariat: rue de Stassart 35, B - 1050 Brussels 2006 CENELEC - All ri
6、ghts of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. No. EN 62373:2006 E ICS 31.080 English version Bias-temperature stability test for metal-oxide, semiconductor, field-effect transistors (MOSFET) (IEC 62373:2006) Essai de stabilit de temprature en polarisa
7、tion pour transistors effet de champ mtal-oxyde-semiconducteur (MOSFET) (CEI 62373:2006) Stabilittsprfung unter Temperatur-Spannungs-Beanspruchung fr Feldeffekttransistoren mit Metalloxid-Halbleiter (MOSFET) (IEC 62373:2006) This European Standard was approved by CENELEC on 2006-08-01. CENELEC membe
8、rs are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on applicatio
9、n to the Central Secretariat or to any CENELEC member. This European Standard exists in three official versions (English, French, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat ha
10、s the same status as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium, Cyprus, the Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, the Netherlands, Norwa
11、y, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland and the United Kingdom. Foreword The text of document 47/1862/FDIS, future edition 1 of IEC 62373, prepared by IEC TC 47, Semiconductor devices, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as
12、EN 62373 on 2006-08-01. The following dates were fixed: latest date by which the EN has to be implemented at national level by publication of an identical national standard or by endorsement (dop) 2007-05-01 latest date by which the national standards conflicting with the EN have to be withdrawn (do
13、w) 2009-08-01 _ Endorsement notice The text of the International Standard IEC 62373:2006 was approved by CENELEC as a European Standard without any modification. _ EN 62373:2006 2 3 EN 62373:2006 CONTENTS INTRODUCTION.4 1 Scope 5 2 Terms and definitions .5 3 Test equipment.7 3.1 Equipment.7 3.2 Requ
14、irement for handling.7 4 Test sample .8 4.1 Sample8 4.2 Packaging .8 4.3 ESD protection circuit 8 5 Procedure 9 5.1 Initial measurement and read point measurement.9 5.2 Test 9 5.3 Notes for field MOSFET.10 5.4 Judgment 11 Annex A (informative) Wafer level reliability test (WLR test)12 Bibliography .
15、13 Figure 1 VGS-IDScurve to explain Vth-ex.6 Figure 2 Connection between MOSFET electrodes and external terminals.8 Figure 3 Example of ESD protection circuit.9 Figure 4 MOSFET BT test circuit (Nch).10 EN 62373:2006 4 INTRODUCTION Under the stress of high temperature, and when high gate-source volta
16、ge is applied over a long period of time, MOSFET degrades; saturation current decreases and the absolute value of threshold voltage increases. Known causes of degradation include mobile ion contamination, charge damage and the creation of interface traps at SiO2/Si interface or fixed charge by the c
17、arrier flow into the oxide. 5 EN 62373:2006 BIAS-TEMPERATURE STABILITY TEST FOR METAL-OXIDE, SEMICONDUCTOR, FIELD-EFFECT TRANSISTORS (MOSFET) 1 Scope This International Standard provides a test procedure for a bias-temperature (BT) stability test of metal-oxide semiconductor, field-effect transistor
18、s (MOSFET). 2 Terms and definitions For the purposes of this document, the following terms and definitions apply. 2.1constant current threshold voltage Vth-cigate-source voltage at which drain current is equal to 0,1 A/m times gate width in micron with the drain-source voltage in linear region or in
19、 the typical value of recommended operating condition NOTE This definition is expressed by the following equation as GScithVV =(1) where, VGSis the gate-source voltage under the following condition: WI = A/m1,0DS(2) where IDSis the drain-source current and Wis the gate width in microns and the drain
20、 voltage is in linear region or in the typical value of recommended operating condition. Linear region means VDS= 0,05,0,1 V (approximately). 2.2 extrapolated threshold voltage Vth-extgate-source voltage which is the extrapolated value in the (linear) IDS-(linear)VGScurve, from the point where the s
21、lope of the IDS-VGScurve becomes maximum with the maximum slope to the point of IDS = 0 in the condition of drain-source voltage in linear region or in the typical value of recommended operating condition NOTE Figure 1 shows the gate-source voltage (VGS)drain-source current (IDS) curve. At about VGS
22、= 0,3 V, the slope of IDS-VGSbecomes maximum. The dotted line is the extrapolated line whose slope is the same maximum value as the IDS-VGScurve. The value where the extrapolated line crosses the line of IDS = 0 (X-axis) is Vth-ext. EN 62373:2006 6 0,00E+0 5,00E04 1,00E03 1,50E03 2,00E03 2,50E03 3,0
23、0E03 3,50E03 4,00E03 0 0,5 1 1,5 2VGSVth-exIDSIEC 1181/06Figure 1 VGS-IDScurve to explain Vth-ex2.3 saturated drain current IDS, satdrain current on condition that both drain-source voltage and gate-source voltage are equal to typical supply voltage of recommended operating condition 2.4 linear drai
24、n current I D, lindrain current on condition that drain-source voltage ranges from 0,05 V to 0,1 V and gate-source voltage is equal to typical supply voltage of recommended operating condition 2.5 drain leakage current ID, leakdrain current on condition that drain-source voltage is equal to typical
25、supply voltage of recommended operating condition and gate-source voltage is zero NOTE If the sub-threshold current is not negligible, gate-source voltage may be equal to substrate (well) voltage. 2.6 maximum transconductance Gm, maxmaximum slope of drain-source current and gate-source voltage curve
26、 with the drain-source voltage in linear region or the typical value of recommended operating condition 2.7 gate leakage current Igleakage current flowing in the gate terminal of an oxide-insulated gate 7 EN 62373:2006 2.8 breakdown voltage VBDSS drain-source voltage when the specified drain leakage
27、 current flows in the grounded gate and source 2.9 substrate leakage current Isubcurrent flowing in the substrate terminal of FET 2.10 oxide electric field Eoxelectric field in the gate oxide NOTE The general formula for Eox is Eox= Vox / tox(3) where Voxis the oxide voltage and toxis the oxide thic
28、kness. toxis determined by a consistent, documented method (physical measurement method by SEM,TEM or CV analysis). It is important to point out that the applied voltage is not necessarily the voltage across the oxide. Ultrathin oxides exhibit quantum confinement effects and gate electrode depletion
29、 effects effectively reducing the voltage across the oxide. The method of determining toxor a reference to the documented standard should be included in the data report. 2.11 electric acceleration factor for 1/E model B slope of the log (lifetime)-1/Eoxcurve 2.12 electric acceleration factor for E m
30、odel D slope of the log (lifetime)-Eoxcurve 3 Test equipment 3.1 Equipment 3.1.1 High temperature oven The wafer prober, equipped with a hot chuck, is used for the wafer level reliability test (WLR test). 3.1.2 Measurement equipment Measurement instruments shall be provided for evaluating the DC cha
31、racteristics of MOSFETs. 3.2 Requirement for handling All measurements that are used for ESD protection shall apply. For example, a wrist strap for ESD protection shall be used. EN 62373:2006 8 4 Test sample 4.1 Sample One MOSFET is used, described as follows: 4.1.1 Channel length (gate length) A mi
32、nimum channel length for the targeted technology shall be used. Longer channel length may be added if necessary. 4.1.2 Channel width (gate width) Any channel width can be used. A channel width measuring 3 m to 20 m is recommended, unless another channel width is essential. 4.1.3 Structure It is reco
33、mmended that four electrodes (gate, source, drain, substrate) be connected to individual external terminals of the packaging. 4.1.4 Wafer process It is strongly recommended that the wafer process such as impurity concentration, thermal treatment or the wiring process be identical to the targeted tec
34、hnology. 4.2 Packaging Any packaging type is acceptable. Packaging is not needed for the WLR test. G D D B D S G D S B IEC 1182/06 IEC 1183/06Figure 2a Recommended Figure 2b Not recommended Figure 2 Connection between MOSFET electrodes and external terminals 4.3 ESD protection circuit Special attent
35、ion should be paid so that ESD damage does not occur to the samples during the packaging process. It is recommended that an ESD protection circuit is added to the gate electrode. 9 EN 62373:2006 Drain Gate Substrate Source IEC 1184/06Figure 3 Example of ESD protection circuit 5 Procedure 5.1 Initial
36、 measurement and read point measurement Measurement is made upon items described below. It is recommended to select one out of Vth-cior Vth-extand one out of IDS, sator ID, lin. Room temperature for electrical measurement shall be ambient. In the case of WLR, electrical measurement may be carried ou
37、t at stress temperature. Vth-ci : constant current threshold voltage Vth-ext : extrapolated threshold voltage IDS sat: saturated drain current Id, lin : linear drain current Id, leak : drain leakage current Gm, max : maximum transconductance Ig : gate leakage current VBDSS : breakdown voltage Isub :
38、 substrate leakage current (for PMOS) 5.2 Test The conditions for the stress test are described below. Temperature, electric field, read point and final test time values are those used for a typical case. It is preferable to carry out a pre-stress test to determine the appropriate test condition. Fo
39、r Nch MOSFET, the gate electrode is biased to positive. For Pch MOSFET, the gate electrode is biased to negative. It is preferable to test polarity for both Nch and Pch. For the Go/NoGo test, the temperature and the electric field may be one point, respectively. If the projected life time is of conc
40、ern, the temperature and the electric field may be more than two points, respectively, to obtain the activation energy and electric field acceleration factor. 5.2.1 Stress temperature The recommended range is 150 C to 250 C. EN 62373:2006 10 5.2.2 Eoxelectric field strength The recommended range is
41、4 MV/cm to 8 MV/cm. For the Nch MOSFET, the gate electrode is biased to positive. For the Pch MOSFET, the gate electrode is biased to negative. Source, drain and substrate (well) are connected to ground. The bias is applied between the gate and ground (see Figure 4). IEC 1185/06Figure 4 MOSFET BT te
42、st circuit (Nch) 5.2.3 Measure point (recommendation) The initial measure point shall be 0 h. Read points: 0,5 h; 1 h; 2 h; 4 h; 10 h; 20 h; 40 h. 5.2.4 Final test time Purpose Final test time Go/NoGo test 1h,10 h (recommended) Lifetime estimation 10 h, 1 000 h (recommended)5.3 Notes for field MOSFE
43、T Field MOSFET can be tested in a similar manner with the following considerations. 5.3.1 Channel length (gate length) Channel length is the minimum isolation length of the targeted technology. Longer channel lengths may be added if necessary. 5.3.2 Electrical characteristics Most of the electrical
44、characteristics may be immeasurable except for Vth-cior ID, leakat typical supply voltage. 5.3.3 Stress electric field Typically, the stress electric field is smaller than that of the nominal MOSFET test because the thickness of the field oxide is thicker than that of the gate oxide. It is recommend
45、ed that the gate-source voltage of the field MOSFET is twice that of the usual supply voltage. 11 EN 62373:2006 5.4 Judgement Calculate the Vthshift from its initial value or relative change of other parameters (except for ID, leak). For the Go/NoGo test, the Vthshift or other parameter change is co
46、mpared with pre-defined criteria. If the shift or the change exceeds the criteria, a “fail” judgment is made. An example of the pre-defined criteria is Vth= 0,1 V or IDS, sat / initial IDS, sat= 10 %. To obtain the projected lifetime, lifetime is calculated with an activation energy and electric fie
47、ld acceleration factor. Though the allowable degradation which defines the lifetime is dependent on the circuit design or the field use condition, typical allowable degradation is Vth= 0,1 V or IDS, sat / initial IDS, sat= 10 %. The relation between lifetime, temperature and electric field is give b
48、y Equation (4) or Equation (5). The electric field acceleration model is different between Equation (4) and Equation (5). Because it is still unknown which one is correct, it is recommended to confirm the acceleration model by additional electric field dependency experiments. =OXexpKexpAaEBTE (4) wh
49、ere Ea is the activation energy (eV) (typically, 1 eV); K is the Boltzmann constant (8,62e 5 eV/K); T is the temperature (K); B is the electric acceleration factor (MV/cm), typically, 50100 MV/cm; Eox is the electric field (MV/cm); A is the constant. () (5) OXexpKexpCaEDTE= where D is the electric acceleration factor (cm/MV); C is the constant. EN 62373:2006 12 Annex A (informative) Wafer level reliability test (WLR test) A.
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