ETSI ETS 300 233 AMD 1-1995 Integrated Services Digital Network (ISDN) Access Digital Section for ISDN Primary Rate《综合业务数字网(ISDN) ISDN基群速率接入数字段》.pdf

1、STD-ETSI ETS 300 233 AND 1-ENGL 1775 m 3400855 021ib;lbZ bb2 H AMENDMENT ETS 300 233 AI March 1995 Source: ETSI TC-TM Reference: REiTM-03046 UDC: 621.395 Key words: ISDN, primary rate access digital section, testing This amendment AI modifies the European Telecommunication Standard ETS 300 233 (1 99

2、4) Integrated Services Digital Network (ISDN); Access digital section for ISDN primary rate ETSI European Telecommunications Standards Institute ETSI Secretariat Postal address: 06921 Sophia Antipolis Cedex - FRANCE Office address: Route des Lucioles - Sophia Antipoiis - Valbonne - FRANCE Tel.: + 33

3、 92 94 42 O0 - Fax: + 33 93 65 47 16 European Telecommunications Standards Institute 1 995. All rights reserved. No part may be reproduced except as authorised by written permission. The copyright and the foregoing restriction on reproduction extend to all media in which the information may be embod

4、ied. STD*ETSI ETS 300 233 AMD 1-ENGL 1775 3LiO0855 021b7bl 5T9 W page2 ETS 300 233: May 1994/A1: March 1995 Whilst every care has been taken in the preparation and publication of this document, errors in content, typographical or otherwise, may occur. If you have comments concerning its accuracy, pl

5、ease write to “ETSI Editing and Standards Approval Dept.“ at the address shown on the title page. STD-ETSI ETS 300 233 AMD 1-ENGL 1795 = 3400855 021b7b4 435 Page 3 ETS 300 233: May 199411: March 1995 Foreword This amendment to ETS 300 233 (19941 has been produced by the Transmission and Multiplexing

6、 (TM) Technical Committee of the European Telecommunications Standards Institute (ETSI). This amendment provides the annex C, which was left “To be provided“ in ETS 300 233 (1 9941. Amendment Page 74, annex C Replace the current annex C “To be provided“ with the following annex C. Annex C (normative

7、): Conformance test principles for the ISDN primary rate access digital section C.l Scope and general information C. 1.1 Scope of this annex This annex provides the test principles for the requirements of this ETS used to determine the compliance of an implementation under test to this ETS. This ann

8、ex does not specify test related to: - safety requirements; - interface or equipment overvoltage protection requirements; - immunity requirements against electromagnetic interferences; - emission limitation requirements. Detailed test equipment accuracy and the specification tolerance of the test de

9、vices is not a subject of this annex. Where such details are provided then those test details are considered as being an informative addition to the test description. The test configurations given do not imply a specific realisation of test equipment, or arrangement, or the use of specific test devi

10、ces for conformance testing. However, any test configuration used shall provide those test conditions specified under “system state“, “stimulus“ and “monitor“ for each individual test. C.1.2 General information For conformance test of the access digital section two relevant test points have to be id

11、entified: - the T reference point covered by ETS 300 O1 1 11; - the V3 reference point. This annex is applicable to interfaces T and V3 as appropriate. The field of application is given at the beginning of each test. As the transmission system is not specified in this ETS, only relevant signals insi

12、de the primary rate stream need to be checked. The coding and the frame organization of this bit stream is outside the scope of this ETS. STD-ETSI ETS 300 233 AMD 1-ENGL 1995 3400855 02Lb7b5 371 Page 4 ETS 300 233: May 1994/A1: March 1995 C.1.2.1 Additional information to support the test The V3 int

13、erface is required to be a standard CCITT Recommendation G.703 81 interface (either 1 20 SZ balanced or 75 unbalanced) according to CCITT Recommendation Q.512 41. If the V3 reference point is not implemented as an interface, a suitable means such as either a local exchange or a Conformance Test Adap

14、tor (CTA) enabling the monitoring of the V1 reference point and giving access to the B and D channels shall be provided by the manufacturer. C. 1.2.2 Abbreviations For the purpose of this annex the following additional abbreviations apply: FAS I UT MF MFAS PRBS Rx SMF Tx Frame Alignment Signal Item

15、Under Test Multiframe Multiframe Alignment Signal Pseudo Random Bit Sequence interface signal Receiver (of the IUT or simulator) Sub-Multiframe interface signal Transmitter of the IUT or simulator C.1.2.3 Definitions For the purpose of this annex the following additional definitions apply: Primary r

16、ate access Digital Section (DS): the provision to transmit a digital signal of specified rate between two consecutive reference points. The term should be qualified by the type of access supported, or by a prefix denoting the V interface at the digital section boundaries. For example: - basic rate a

17、ccess digital section; - primary rate access digital section; - V, digital section. Item Under Test (IUT): Implementation of interfaces related functions for: - the user side interface (T), i.e. NT1; and - the exchange side interface (V31, i.e. LT. Simulator (terminal equipment, exchange): device ge

18、nerating a stimulus signal conforming to this ETS to bring the IUT into the required operational state and monitoring the receive signal from the IUT. It can either be a simulator for the user side or the exchange side of the interface. C.1.3 Connection of the simulator to the IUT For testing the el

19、ectrical characteristics of the IUT, the simulator, or its relevant part, shall be connected directly to the interconnecting points for the interface wiring at the IUT unless otherwise stated. All other tests may be performed with interface wiring complying with the requirements given in CCITT Recom

20、mendation G.703 81 and in ETS 300 O1 1 l 1, table 1, clause 7. STD.ETSI ETS 300 233 AMD 1-ENGL 1975 3400855 021b7bb 208 Page 5 ETS 300 233: May 19941A1: March 1995 C.1.4 Allocation of test Relevant interface T, V3, or T and V3 One test definition may cover more than one requirement for one or both i

21、nterface points (interface T or V31. Requirements which do not need specific test definition are indicated by “N/R“ (Not Relevant). Requirements which are not relevant for this ETS and which require testing defined by other ETSs are indicated by “NIA“ (Not Applicable). C. 1.4.1 General Test defined

22、in Table C. 1 : General requirements Relevant interface T. V3, or T and V3 Functions Scope Normative references Definitions and abbreviations Definitions Abbreviations Test defined in Clausel subclause 1 2 3 3.1 3.2 N/R N/R N/R N/R N/R C. 1.4.2 Type of configuration and applications requirements Tab

23、le C.2: Type of configuration and applications requirements Functions Configuration and application Configuration Application Modelling and relationship between the access DS and the ET Clause/ subclause 4 4.1 4.2 4.3 N/R N/R N/R STD-ETSI ETS 300 233 AMD 1-ENGL 1775 3400855 021b7b7 144 Page 6 ETS 30

24、0 233: May 1994lA1: March 1995 C. 1.4.3 Functional characteristics requirements Table C.3: Functional characteristics requirements Functions Function B-channel HO-channel H 1 -channel D-channel Bit timing Octet timing Frame alignment CRC-4 procedure M channel Power feeding Operation and maintenance

25、of access digital section Clausel subclause 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.1 1 Relevant interface T. V3. or T and V3 N/R T and V3 T and V3 T and V3 T and V3 T and V3 T and V3 T and V3 T and V3 T and V3 T T and V3 Test defined in C.2.1 and C.2.5.5 C.2.1 and C.2.5.5 C.2.1 and C.2.5.5 c.2

26、.1 c.2.5 :.2.3, C.2.3.3, and c.2.5.5 C.4.1 C.4.2 c.2.1 C.5.1 C.3.1 STD-ETSI ETS 300 233 AND 1-ENGL 1995 I 3400855 02Lb7bB 080 I Page 7 ETS 300 233: May 1994lA1: March 1995 C. 1.4.4 Signai delay and jitter requirements Table C.4: Signal delay and jitter requirements Functions I Clausel I Relevant int

27、erface subclause I T, V3, or T and V3 Signal transfer delay Jitter Output/lnput jitter at T reference point Jitter at V3 reference point 6 7 7.1 7.2 T and V3 N/R T v3 C.1.4.5 Operation and maintenance Table C. 5: Operation and maintenance requirements Functions 3peration and maintenance Zontrol faci

28、lities Loopbacks Loopbacks implementation il ii 1 Loopback procedure Monitoring Functions Defect conditions and consequent action Detection of defect conditions Clausel subclause 8 8.1 8.1.1 8.1.1.1 8.1.1.2 8.2 8.2.1 8.2.2 8.2.2.1 Relevant interface T. V3. or T and V3 N/R NlR N/R v3 v3 N/R N/R N/R N

29、/R Test defined in C.2.4 C.2.6.1 and C.2.6.3 C.2.6.2 Test defined in C.7.1 C.7.2 c.7 (continued) STD-ETSI ETS 300 233 AND 1-ENGL 1445 3400855 02lb7h9 T17 Page 8 ETS 300 233: May 1994/A1: March 1995 Table C. 5 (continued): Operation and maintenance requirements Functions Definition of defect indicati

30、on signals - Frames - Substituted frames - NF - LFA Loss of power in NT1 or LT - AUXP Detection of defect indication signals - LOS or LFA at line side o NT 1 . LOS at line side of LT . Loss of power at NT1 . AIS at line side of NT1 . LOSatV3 . LOSatT . Loss of power at T 3efinition of detection algo

31、rithm NOF LFA Loss of signal at T and V3 AIS Loss of power in the NT1 Loss of power in the LT zonsequent action Irror performance monitoring lperation and maintenance irocedures anitioning of function )efinitions of signals at T eference point lefinitions of signals at V3 eference point Clausel subc

32、lause 8.2.2.2 8.2.2.3 8.2.2.4 8.2.2.5 8.3 9 9.1 9.2 9.3 (continued) Relevant interface T. V3. or T and V3 T and V3 T and V3 v3 T and V3 T and V3 T and V3 v3 v3 v3 v3 v3 T and V3 T and V3 T and V3 T and V3 T and V3 T and V3 T and V3 T and V3 T and V3 v3 N IR N/R N/R N/R Test defined in c.2.2 C.6 C.3.

33、1 and (2.6.4 C.3.1 C.3.1 and C.6.6 C.6.8 C.8.3 C.8.8 C.8.6 C.2.5.1 C.6.3 C.6.2 C.3.1 c.2.1 c.4.3 C.3.1 and C.6.1 (2.3.1 C.3.1 and C.6.6 (2.3.1 C.6 C.4.2 and C.4.3 - STD-ETSI ETS 300 233 AMD 1-ENGL I995 3400855 022b77U 739 Clause/ subclause table 2 table 3 (continued) Page 9 EIS 300 233: May 1994/A1:

34、 March 1995 Relevant interface Test defined in T, V3, or T and V3 v3 C.2.2 and C.6 NIA v3 C.3.1 and C.6 T and V3 T and V3 NIA T and V3 T and V3 T and V3 T and V3 C.3.1, C.4.1, and C.6.2 C.3.1 and C.6.3 C.3.1 and C.6.4 C.3.1 and C.6.5 C.3.1 and C.6.6 C.6.7 and C.6.2 v3 C.6.8 and C.3.1 v3 C.3.1 and C.

35、2.5.1 v3 C.2.5.1 N/A N/A v3 c.7 v3 c.7 v3 c.7 v3 c.7 Table C. 5 (continued): Operation and maintenance requirements Functions I FES related to operation and maintenance - normal DS- ET - normal DS NOF Loss of frame alignment and frame alignment with simulated FAS, BIT 2 = 1, FAS ff I FRAME B BIT 2 =

36、 O, FAS, BIT 2 = O, FAS, BIT 2 = 1, FAS BIT 2 = O, FAS, BIT 2 = O, FAS, BIT 2 = O, FAS BIT 2 = 1, FAS NOF # RAI or NOF (note 2) # NOF t frame alignment word NOF #4to8ms RAI and back to NOF will occur No MF alignment on the I (if MF alignment is operating I simulated frame alignment word properly), (

37、note 3) No further RAI shall occur within a time period of 20 ms - - NOTE 1: This stimulus shall be repeated in order to allow clock synchronisation of the IUT, the time taken to synchronise may be dependent on the implementation. NOTE 2: RAI or NOF depending on the implementation options described

38、in CCIn Recommendation G.706 71, subclause 4.1.1 and ETS 300 O1 1 ill, clause 5. NOTE 3: The vertical bar indicates that the given monitor result shall appear at least once during application of the stimulus. STD-ETSI ETS 300 233 AMD I-ENGL 1995 3400855 021b708 779 II TX 1 ! I RE F. POINT ! ! i SIMU

39、LATOR T I RX : ! . * POWER . SOURCE Page 27 ETS 300 233: May 1994lA1: March 1995 i i ! j i i , RX TX : RX SIMULATOR ! IUT v3 j REF.POINT I TX RX 1 TX POWER SINK C.4.2 CRC MF alignment Test applicable at T and V3 reference point. Purpose: To test if the IUT correctly executes the CRC MF alignment. Te

40、st configuration: System state: Stimulus: Monitor: Results: Figure C. 14: Test configuration for CRC MF alignment Various states. Consecutive correct and errored CRC MF alignment signais from the simulator, i.e. bit 1 in frames not containing the FAS as given below. Output signal from the IUT as giv

41、en below. As listed in table C.l 1. STD-ETSI ETS 300 233 AMD L-ENGL 1795 3400855 0236787 805 Page 28 ETS 300 233: May 1994/A1: March 1995 STIMULUS FRAME B (note 1) # Table C.11 MONITOR COMMENT NOF IFAS, BIT 2 = 1, IFAS, BIT 2 = 1, IFAS, BIT 2 = 1 MF A 4XMFB MF A 37XMFB RAI Initial condition NOF RA I

42、 No MF alignment NOF NOF, transition to RAI and back 2 MFAS within 8 ms in the lirnii MF A, MF B, MF A, MF B, MF A, MF B I I MF B I NOF to NOF (note 2) NOF of 100 ms # 251 IFAS, BIT 2 = 1 , IFAS, BIT 2 = 1, IFAS, BIT 2 = 1 MF B Stable NOF RA I Initial condition NOF No RAI 500 ms after a loss of MF a

43、lignment Correct frame alignment but not # 250 MF B # I I NOTE 1: This stimulus shall be repeated in order to allow clock synchronisation of the IUT, the time taken to synchronise may be dependent on the implementation. The vertical bar indicates that the given monitor result shall appear at least o

44、nce durina amlication of the stimulus. NOTE 2: - MF alignment No MF alignment within 500 ms RA I C.4.3 CRC processing Test applicable at T and V3 reference points. MFA, 4 X MF B MF A, 2 X MF B, MF A MFA, 2 X MF B, 2 X MF A MFB. MFA Purpose: RA I NOF MF alignment reached NOF Undefined condition Test

45、configuration: I TX To test the correct execution of CRC calculation, comparison with the received bits C1 to C4 and generation of the CRC error report with bit E. I RX TX, i IUT : 1 I TX RX 1 i POWER 1 SINK i RX SIMULATOR v3 REF.POINT TX - j SIMULATOR 1 REF.POINT : POWER SOURCE T Figure C. 1 5: Tes

46、t configuration for CRC processing STD.ETSI ETS 300 233 AND 1-ENGL 1775 3400855 02Lb 527 Page 29 ETS 300 233: May 19941A1: March 1995 System state: State DS 1.1 1 (normal operation). Stimulus: Monitor: Results: SMF A and SMF B at interface of the test as given below. Output signal at the IUT, i.e. E

47、 bits as given below. As listed in tables C. 12 and C. 13. A CRC error report, indicated by an E bit set to ZERO, shall be received within 1 s after the generation of a SMF in error. Definition of a SMF in error is given in CCITT Recommendation G. 704 31, subclause 2.3.3.5.3. Table C. 12 SMF B with

48、E bit set to ZERO lone E bit set to ZERO IFE Y NOTE: Due to possible delay FE G may not be generated. STD*ETSI ETS 300 233 AND 1-ENGL 1795 B 3Y00855 021b77L 4b3 STIMULUS at V3 ref. point SMF A SMF B SMF A SMF B, SMF B SMF A 914 X SMF B # Repeat more than 1 s # Repeat more than 1 s Page 30 ETS 300 23

49、3: May 1994/A1: March 1995 MONITOR T V3 (DS - ET) NOF NOF NOF NOF NOF NOF FE A (no E bit set to ZERO) FE U (one E bit set to ZERO) FE A (no E bit set to ZERO) FE U (two E bits set to ZERO) FE A (no E bit set to ZERO) 9 14 contiguous E bits set to Table C.13 SMF A 915 X SMF B 85 X SMF A # Repeat more than 1 s ZERO FE A (no E bit set to ZERO) NOF Temporarily AIS (note 2) TemDorarilv FE E 915 X SMF 8 SMF A # FE G (notel) FE A (no E bit set to ZERO) NOF I /FAS, BIT 2 = 1, IFAS, I AIS I FE E (no E bit set to ZERO) BIT 2 = 1, /FAS, BIT 2 = 1