GEIA SSB-1 004-A-2009 F ailure Rate Estimating Annex to SSB-1 Guidelines for Using of Plastic Encapsulated Microcircuits and Semiconductors in Military Aerospace and Other Rugged A.pdf

1、 TechAmerica Engineering Bulletin SSB-1.004-A Failure Rate Estimating SSB-1.004-A (Annex to SSB-1, Guidelines for Using of Plastic Encapsulated Microcircuits and Semiconductors in Military, Aerospace and her Rugged Applications) OtApril 2009 Copyright Government Electronics it involves identificatio

2、n and classification of failure mechanisms, development and use of monitors, and investigation of failure kinetics allowing prediction of failure rate at use conditions. Failure kinetics are the characteristics of failure for a given physical failure mechanism, including (where applicable) accelerat

3、ion factor, derating curve, activation energy, median life, standard deviation, characteristic life, instantaneous failure rate, etc. The failure rate of semiconductor devices is inherently low. As a result, the semiconductor industry uses a technique called accelerated testing to assess device reli

4、ability. Elevated stresses are used to produce the same failure mechanisms as would be observed under normal use conditions, but in a shorter time period. Acceleration factors are used by device manufacturers to estimate failure rates based on the results of accelerated testing. The objective of thi

5、s testing is to identify these failure mechanisms and eliminate them as a cause of failure during the useful life of the product. This document provides reference information concerning methods commonly used by the semiconductor industry to estimate failure rates from accelerated test results. These

6、 methods are frequently used by OEMs in conjunction with physics of failure reliability analysis to assess the suitability of plastic encapsulated microcircuits and semiconductors for specific end use applications. 2 Reference Documents SSB-1.002 Environmental Tests and Associated Failure Mechanisms

7、 SSB-1.003 Acceleration Factors 1 Copyright Government Electronics a complete sub-system level failure rate estimate would, of course, include the failure rates for all components included in the sub-system. Upon reviewing device manufacturers product reliability reports for each device used in the

8、sub-system, we note the test conditions, device-hours, and number of failures from the applicable acceleration tests. We use sub-system level (e.g. circuit board) thermal analysis results to establish use condition junction temperatures (Tu) for each device. Using the methods described earlier, we c

9、alculate the failure rates associated with each environmental effect and then derive an overall failure rate for each device. Finally, we sum the failure rates of all the devices to estimate the sub-system level failure rate. Figure 2 illustrates a sub-system level failure rate estimate. Copyright G

10、overnment Electronics & Information Technology Association Provided by IHS under license with GEIA Not for Resale-,-,-SSB-1.004-A Sub-System Analysis Thermal Effects TemperatureHumidity Effects TOTAL (Ea = 0.7) (Rhu= 0.5) . . . ( = 60) MTTF MTTF Description Ref Des TuTtton t(FIT) TtRHtton th(FIT)Tot

11、al(FIT) (Hours) (Years)Octal Buffer/Driver U36 91 165 1,900,000 0 11.146 85 0.85 814,000 0 370.447 . . . 381.621 2.62E+06 299 Octal Buffer/Driver U41 79 165 1,900,000 0 5.212 85 0.85 814,000 0 139.408 . . . 144.648 6.91E+06 789 Supply Voltage Supervisor U17 100 165 39,108,000 1 2.047 85 0.85 16,410,

12、000 11 502.779 . . . 504.826 1.98E+06 226 Real Time Clock U2 90 150 1,020,000 0 37.671 85 0.85 1,100,000 0 253.314 . . . 291.007 3.44E+06 392 Line Buffer/Driver U103 92 165 2,600,000 0 8.658 85 0.85 1,976,000 0 165.072 . . . 173.748 5.76E+06 657 FPGA U8 102 150 3,370,000 2 79.029 130 0.85 141,900 0

13、190.105 . . . 269.170 3.72E+06 424 Flash Memory U104 86 165 5,972,952 7 23.797 121 1 58,800 0 147.276 . . . 562.018 1.78E+06 203 Flash Memory U105 83 165 5,972,952 7 19.669 121 1 58,800 0 115.280 . . . 456.505 2.19E+06 250 Flash Memory U106 79 165 5,972,952 7 15.180 121 1 58,800 0 82.622 . . . 345.8

14、33 2.89E+06 330 Flash Memory U107 75 165 5,972,952 7 11.646 121 1 58,800 0 58.765 . . . 262.058 3.82E+06 436 RS-232 Driver/Receiver U18 93 125 1,608,840 0 95.755 121 1 307,488 0 49.104 . . . 144.888 6.90E+06 788 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

15、. Registered Transceiver U196 91 155 2,600,000 0 12.559 85 0.85 1,976,000 0 152.603 . . . 165.179 6.05E+06 691 Registered Transceiver, U197 89 155 2,600,000 0 11.103 85 0.85 1,976,000 0 130.250 . . . 141.370 7.07E+06 807 E-PROM U35 91 145 178,988 0 287.173 121 1 4,320 0 2988.334 . . . 3369.260 2.97E

16、+05 34 FPGA U26 96 145 423,433 1 362.421 121 1 18,816 0 1011.791 . . . 1374.441 7.28E+05 83 TOTAL 1412.744 16765.038 . . . 18191.157 5.50E+04 6 Figure 2 Illustration of a Sub-System Level Failure Rate Estimate 15 Copyright Government Electronics & Information Technology Association Provided by IHS u

17、nder license with GEIA Not for Resale-,-,-SSB-1.004-A 5 Deriving Acceleration Test Parameters from Use Condition Parameters and Sub-System Failure Rate Requirements One can reverse this methodology to derive test parameters necessary to achieve a specific failure rate allocation for a particular end

18、 use environment. The following subsections illustrate: 5.1 Temperature-Humidity-Bias Effects (HAST Test Extrapolation) In this example, the MTTF allocation for a device, at 95% confidence, is 35 years (i.e., 3,266 FIT) for temperature-humidity-bias related failure mechanisms in use conditions of 60

19、C and 90%RH. We plan to perform HAST test at 130C and 85%RH to qualify the device for temperature-humidity-bias effects in this environment. In this use environment, the Hallberg-Peck model yields the following acceleration factor: =tuautTTkERHRH11exp3fA 19516.2731=13016.273851106171.89.0exp9.085.05

20、3+=Using the table, the chi-square distribution function (2) for one failure at a confidence level of 95% is 9.488. The failure rate estimate becomes: ()FITttAfth 266,0310195229=fd488.910,92= Solving for device-hours (t), this equation becomes: 450,710266,31952488.99=t The HAST test, therefore, must

21、 accumulate 7,450 device-hours. If we apply a 5 per cent LTPD to provide some protection against any significant level of freak defects, we could perform HAST test with samples of n = 77, c = 1. This corresponds to HAST test duration of 7,450 / 77 = 97 hours. If we apply a 5 per cent LTPD, but perfo

22、rm HAST test with samples of n = 45, c = 0, the HAST test duration becomes 7,450 / 45 = 166 hours. 16 Copyright Government Electronics & Information Technology Association Provided by IHS under license with GEIA Not for Resale-,-,-SSB-1.004-A 5.2 Thermo-mechanical Effects (Thermal Cycling Test Extra

23、polation) In this example, cyclic thermal stress conditions over the anticipated product life are shown in Table 4. We plan to perform Temperature-Cycling test from -55C to 125C (Tt= 180C) to qualify the device for thermo-mechanically induced defects. Using the Coffin-Manson Relationship with a cons

24、ervative value for the constant (m = 3), we estimate the number of failure free test cycles associated with each condition. Table 4 Cyclic Thermal Stress Conditions over the Anticipated Product Life Temperature Change (Tu) Service Conditions Number of Cycles (N) (a) 20 Yr. Controlled Storage 10C 7,3

25、00 (b) 2 Yr. Uncontrolled Storage 60C 730 (c) 90 Days Operating 60C 90 (a): 20 Years Controlled Storage: 832,5101803=mutfaTTA25.1832,5300,7 =faaaANN(b): 2 Years Uncontrolled Storage: 27601803=mutfbTTA03.2727730 =bbANNfb(c): 90 Days Operating: 271803=mtfcTA33.360 uT27 =fccA3261.3133.303.2725.1 =+=+=

26、cbaTotal90cNNThe minimum number of failure free cycles in our -55C to 125C Temperature-Cycling test, therefore, is: N N N N 17 Copyright Government Electronics & Information Technology Association Provided by IHS under license with GEIA Not for Resale-,-,-SSB-1.004-A 18 This page blank. Copyright Go

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