ITU-T G 192-1996 A Common Digital Parallel Interface for Speech Standardisation Activities - General Characteristics of International Telephone Connections and International Teleph.pdf

1、 ITU-T RECMN*G.192 96 4862591 Ob35229 689 INTERNATIONAL TELECOMMUNICATION UNION ITU-T TELECOMMUNICATION STANDARDIZATION SECTOR OF ITU G.192 (03/96) GENERAL CHARACTERISTICS OF INTERNATIONAL TELEPHONE CONNECTIONS AND INTERNATIONAL TELEPHONE CIRCUITS A COMMON DIGITAL PARALLEL INTERFACE FOR SPEECH STAND

2、ARDISATION ACTIVITIES ITU-T Recommendation G.192 (Previously “CCIlT Recommendation”) FOREWORD The -T (Telecommunication Standardization Sector) is a permanent organ of the International Telecommunication Union TU). The -T is responsible for studying technical, operating and tariff questions and issu

3、ing Recommen- dations on them with a view to standardizing telecommunications on a worldwide basis. The World Telecommunication Standardization Conference (WTSC), which meets every four years, establishes the topics for study by the -T Study Groups which, in their turn, produce Recommendations on th

4、ese topics. The approval of Recommendations by the Members of the ITU-T is covered by the procedure laid down in WTSC Resolution No. 1 (Helsinki, March 1-12, 1993). ITU-T Recommendation G.192 was prepared by ITU-T Study Group 15 (1993-1996) and was approved under the WTSC Resolution No. 1 procedure

5、on the 19th of March 1996. NOTE In this Recommendation, the expression “Administration” is used for conciseness to indicate both a telecommunication administration and a recognized operating agency. O IW 1996 All rights reserved. No part of this publication may be reproduced or utilized in any form

6、or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the ITU. ITU-T RECMN*G-192 96 = 48625911 Ob1152311 237 = CONTENTS 1 Scope 2 Introduction 3 Definitions 4 General Description of the Digital Parallel Interface . 4.1 Logical Description

7、 4.2 Master Clock and Reset 4.3 Timing, Timeslots and Capacity . 4.4 Reset procedure - 5 Hardware implementation Connector type, pin assignment and cabling Line drivers and receiver termination . 5.3 Distributed multiplexer . Signal delays within devices . Annex A - DPI implementation using TTL logi

8、c integrated circuits Annex B - Data formats B.2 Coded bitstream Annex C - Rules for codec implementation Annex D - Example host laboratory test configurations . 5.1 5.2 5.4 B.l Time signals Appendix I - The ITWT 8 kbit/s speech codec test parallel interface Specialisation of the interface . I . 1 1

9、.2 Data formats References . Recommendation G.192 (03/96) Page 1 1 1 2 3 3 4 5 5 5 5 5 9 9 12 13 14 15 15 17 17 18 18 1 ITU-T RECMM*G-L92 9b 4862573 Oh35232 I173 ABSTRACT This Recommendation defines the physical, electrical and logical specification of a digital parallel interface which is to be use

10、d to interconnect the different devices needed in standardisation activities of speech codecs sponsored by the ITU-T. Included in this Recommendation are the data formats at the input and output of the encoder, decoder and bit manipulation devices. Finally, rules for the implementation of codecs to

11、guarantee proper interoperation of devices interconnected using that digital parallel interface are presented. ii Recommendation G.192 (03/96) ITU-T RECMN*G.L92 9b = 4862593 Oh35233 OOT Recommendation G. 192 A COMMON DIGITAL PARALLEL INTERFACE FOR SPEECH STANDARDISATION ACTIVITIES (Geneva, 1996) 1 S

12、cope This Recommendation describes a 16-bit parallel input and output interface for the interconnection of test and reference devices in IT-T standardisation activities. 2 Introduction The history of the Digital Parallel Interface PI) specification goes back to the CCITT wideband speech 64 kbit/s co

13、dec tests that led to the present Recommendation G.722, where a similar parallel interface was used. That interface was simplified to fit into a 25-pin connector for the host laboratory sessions of the subjective tests of the GSM full rate codec. This simplified interface has also been used in the s

14、tandardisation of the second generation GSM system and in the standardisation of the -T 8 kbit/s speech coder. The interface is simple to build and easy to use and, compared to a serial interface, allows for a simpler access to the data flow for monitoring and measuring codec parameters, e.g. delay

15、and timing. This Recommendation is structured as follows: initially an overview of the principles of the interface is given, with a functional description of the signals and data lines. Then hardware aspects are considered. Specialisations of the interface are given in the annexes. These specialisat

16、ions involve: the DPI implementation using TTL family integrated circuits; description of data formats based on the type of device where the DPI is employed; device implementation rules when the device is a speech coder; and configuration examples for the DPI. For information, a description of the s

17、pecialisation used for the host laboratory work of the IT-T 8 kbit/s coder is given as an appendix. 3 Definitions For the purposes of this Recommendation, the following definitions and abbreviations apply. 3.1 codec: An encoderidecoder pair. 3.2 coded bitstream signai: One of the possible signal rep

18、resentations on the DPI, in general representing the signal at the output of an encoder, or the input of a decoder. May also be the representation of a communication channel. 3.3 CUT: Codec under Test. 3.4 DPD: Digital Processing Device. 3.5 3.6 to a INTI that occurs together with the Mark signal ac

19、tive (high) and an unmarked INTI when Mark is low. 3.7 LSb: Least Significant bit. 3.8 3.9 MSb: Most Significant bit. DPI: The Digital Parallel Interface defined in this Recommendation. interface timeslot (INTI): A rising-edge to rising-edge time interval of the clock signal. A marked INTI refers ma

20、rk signal (mark): A one-bit signal that indicates whether the data on the data bus is valid or not. Recommendation G.192 (03/96) 1 ITU-T RECMN*G.L72 96 4862573 Ob35234 T4b DPI a 3.10 to the reset operation. normal operation: Mode of operation of the interface used for regular processing by the devic

21、es. Alternative DPI DPI DPI Digital Digital Digital a a Deuce 1 Device 2 Dece 3 I I Processing Processing w Processing 3.11 reset operation: A procedure started when the Reset signal is active for 16 INTIS, and that lasts 1616 INTIS in total. Used to synchronise all the devices in the chain to their

22、 initial reset state. After the end of the Reset Operation, the DPI and the interconnected devices resumeNormal Operation. NOTE- 1616 INTIS represent 1 rns (16 INTIS) plus 100 ms (1600 INTIS) for a 16 kHz clock. 3.12 3.13 devices of the chain. reset: Active-low, one bit signal used to start the Rese

23、t Operation. Rx-Clk: Backwards clock signal. Used to clock devices when the clock master lies in one of the intermediate 3.14 adjusted words. softbit: An element of the coded bitstream signal where logical bits 1 and O are represented by 16-bit right 3.15 erasure purposes. 3.16 Used necessarily betw

24、een data source, data sink, and codecs. synchronisation word: An element of the coded bitstream signal provided for synchronisation and fiame time signai: Another of the possible signal representations on the DPI, in general representing time samples. 3.17 Tx-Clk: Forward clock signal. A continuous-

25、time running signai providing the basic rate of the interconnected devices. 4 General Description of the Digital Parallel Interface Normally, a set of digital test data is processed over different Codecs under Test (CUT) during a standardisation procedure of a speech codec by the -T. Figure 1 shows

26、an example of test configuration where three Digital Processing Devices (DPD) are interconnected by means of the DPI. Each of the DPD have an input and an output DPI. T15 19660-95/6 O1 FIGURE UG.192 A generic test configuration where the DPI is used A set of digital test data (usually digitised spee

27、ch) is sent out synchronously from the data source to the first DPD, what could be the encoding portion of a CUT. Processed data is then sent in an appropriate format to the second DPD in the chain, for example a channel model. After processing by the second DPD, data is sent to the final DPD in the

28、 example chain, what could be the decoding portion of a CUT. Data out of this last DPD is finally collected by the data sink. It should be noted that the data type in the different usages of the DPI in Figure 1 does not need to have the same format. Any number of DPD could be connected in principle,

29、 allowing to build complex structures (e.g. to simulate a tandem of codecs in two different digital cellular mobile systems). Other application examples are given in Annex D. The interface is able to transport in parallel up to 16 bits of Data (DlSDO) from one device (transmitter) to another (receiv

30、er). Valid data words are identified by mark bits. 2 Recommendation G.192 (03/96) ITU-T RECNN*G.L92 96 4862591 0635235 982 m A clock signal is transmitted in parallel with the data lines of the interface in the forward direction (Tx-Clk). A clock signal is also available in the backward direction (R

31、x-Clk), what can be used for special purposes. An active-low /Reset signal is applied for synchronisation of the devices in a chain. 4.1 Logical Description Test hardware configurations may differ in each standardisation process. However, the basic format for the data passing through the DPI is the

32、same. It is composed of 16-bit data words, clocked in and out at a certain rate (e.g. 16 kHz) and marked as valid or invalid by a special mark bit, as indicated in Figure 2. The transmission throughout the test configuration is processed synchronously and the mark bit identifies whether the precedin

33、g device was ready to send out data or not. Figure 3 describes a generic hardware structure for the DPI. All data, mark and clock lines are buffered in both transmitter and receiver ends. The data and mark bits are stored in a parallel register during one interface timeslot. The hardware structure i

34、s independent of the logic family used, but the same family is needed for a given pair transmitter and receiver interconnected ends. If a termination is needed to reduce signal reflections, it needs to be adequate (and possibly specific) to the logic family chosen. - D15 D14 D13 D 2 D3 D2 D1 DO - Ol

35、l 1 1 11 Mark T151867095I602 Inmlid data, dont care o Lowbit 1 High bit FIGURE 2/G.192 Example for a possible data flow in the DPI While Figure 3 display the in rfa e from the point of view of two interconnec rd devices, Figure 4 displays the interface from a giien- devices point of view. There it c

36、an be seen where the algorithm resides, the data lines it is supposed to use, and how the other control signals are routed inside and through the given DPD. Examples are given in Figure 4 for 3 device setups. This figure is further described in 4.2. Currently only a TTL (Transistor-Transistor Logic)

37、 implementation of the basic hardware has been tested and used. Its description is given in Annex A. 4.2 Master Clock and Reset The clock signai for devices interconnected by the DPI must be generated by only one device in the chain. This master clock in the simplest case is provided by the data sou

38、rce. In this case, only a clock line in the forward direction is necessary, i.e. from the data source towards the data sink through the interconnected devices. Recommendation G .192 (03/96) 3 I Reset Direction - I FIGURE 3/G.192 Basic diagram for the hardware implementation of the DPI Reset Directio

39、n i - In other cases, as illustrated in Figure 4, the master clock may be a device somewhere in the chain. This could occur, for example, in connecting a codec to a real channel. In this situation the channel must provide the master clock and reset, and ail other devices must synchronise to the chan

40、nel. The channel has to generate clocks in the forward direction (Tx-Clk) and in the backward direction (Rx-Clk) through the chain. All devices in the chain must be configured to use either RxClk or TxClk, depending on where the master clock is located. See Figure 4 for an example configuration. The

41、 same holds for the reset signai, which a given device must derive either from its output interface (for devices before the master reset) or from its input interface (devices in forward direction). 4.3 Timing, Timeslots and Capacity The data and mark bits are clocked out from the transmitter side on

42、 the rising edge of Tx-Clk and clocked in at the receiver side on the failing edge of Tx-Clk (see Figure 5). An “INterface meslot” (INTI) is defined as one clock period from rising edge to rising edge of the clock signal. Sixteen data bits, numbered DO to D15, and one mark bit are transmitted by eac

43、h INTI. INTIS with mark high (active high) are called “marked”, otherwise they are said to be “unmarked”. The functions of the interface are in principle independent from the clock rate, which can be as high as several MHz, constrained by cable lengths and the logic family of the integrated circuits

44、 used. For telephony codecs, a 16 kHz clock (TxClk) having a 50% duty cycle will be used in most cases. This gives in principle a total capacity of 256 kbit/s (i6 bits x 16 Wz). 4 Recommendation G.192 (03/96) ITU-T RECNN*G.LZ 96 48b259L 0635237 755 If the master device is located within a chain of i

45、nterconnected devices, as in Figure 4, then its input interface sends the RxClk backwards in the chain. The neighbouring backwards device has to regenerate this clock signal and use it as Tx-Clk. Due to possible phase shifts between RxClk and Tx-Clk, the data and mark bits shall always be triggered

46、with the clock line in the forward direction, Tx-Clk. 4.4 Reset procedure The reset signal /Reset is an active-low signal whose purpose is to synchronise all the devices in the chain. In normal operation, Reset shall be inactive (high). The reset signal will be applied by the master reset (e.g. the

47、data source or the channel) to the adjacent device(s) in the chain. For the reset procedure, the steps described below must be followed to guarantee the desired synchronisation. Figure 6 illustrates the signals during the reset procedure. The reset procedure is initiated by switching the reset signa

48、l /Reset to low (active) with the rising edge of TxClk (same as Data and Mark bits). - Every device in the chain has to receive the reset signal at its /Reset input and must regenerate and output the reset signal at its /Reset output (input and output may depend on the location of the master reset).

49、 Ail devices shall test the reset signal with the failing edge of Tx-Clk (same as data and mark bits) and start or continue their specific reset procedure when /Reset is active (low) at that time. The reset signal shall remain active for at least 16 clock cycles (1 ms for a 16 kHz clock) and be switched to inactive (high) with the rising edge of Tx-Clk. This is indicated in Figure 6. The source of data shall wait exactly for another 1600 clock cycles (100 ms for a 16 kHz clock) before the first INTI is marked to transmit the first valid data value (e