ITU-T G 726 APP II-1991 Description of the Digital Test Sequences for the Verification of the G 726 40 32 24 and 16 kbit s ADPCM Algorithm - Series G Transmission Systems and Media.pdf

1、 STD-ITU-T RECMN G-72b APPEND II-ENGL 1771 D 48b2571 Ob37213 7T2 INTERNATIONAL TELECOMMUNICATION UNION ITU-T TELECOMMUNICATION STANDARDIZATION SECTOR OF ITU G.726 Appendix II Test Vectors (03/9 I ) SERIES G: TRANSMISSION SYSTEMS AND MEDIA, DIGITAL SYSTEMS AND NETWORKS Digital transmission systems -

2、Terminal equipments - Coding of analogue signals by methods other than PCM Description of the digital test sequences for the verification of the G.726 40,32, 24 and 16 kbit/s ADPCM algorithm STD-ITU-T RECMN G-72b APPEND II-ENGL 1991 D LiAb2591 Ob3721q 839 = FOREWORD ITU (International Telecommunicat

3、ion Union) is the United Nations Specialized Agency in the field of telecommunications. The ITU Telecommunication Standardization Sector (ITU-T) is a permanent organ of the ITU. The ITU-T is responsible for studying technical, operating and tariff questions and issuing Recommendations on them with a

4、 view to standardizing telecommunications on a worldwide basis. The World Telecommunication Standardization Conference (WTSC), which meets every four years, establishes the topics for study by the ITU-T Study Groups which, in their turn, produce Recommendations on these topics. The approval of Recom

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9、rmission in writing from the ITU. STD.ITU-T RECMN G.72b APPEND II-ENGL 1991 m 4b257L Ob37215 775 DESCRIPTION OF THE DIGITAL TEST SEQUENCES FOR THE VERIFICATION OF THE G.726 40,32,24 AND 16 KBIT/S ADPCM ALGORITHM 1 Introduction This guide describes the test sequences (vectors) for the ADPCM algorithm

10、s of Recommendation G.726 at the four fixed bit rates (16 kbit/s, 24 kbits, 32 kbit/s, 40 kbit/s) for both A-law and p-law. It reproduces mainly the text of the CCITT collective letter No. 1 IKV, dated 21/03/1991, the only amendments corresponding to the grouping on two 3%“ disks of the files which

11、were previously on four 5%“ disks. The tests are arranged in two separate diskettes, one for the p-law and one for the A-law. For each law, the diskette contains the reset test vectors and the homing test vectors. The diskettes are of the 3 ?4 MS-DOS format. Within each diskette, the files are distr

12、ibuted in subdirectories that correspond to individual bit rates for the homing and reset case. A READ.ME file lists the contents of each diskette. 2 General description The verification testing procedure consists in applying an input sequence to an ADPCM implementation and veriQing that the output

13、sequence is the same sequence in the output file for the same test conditions (PCM coding law, type of input, initial state of the implementation). There are three types of input sequences. The first type consists of various sinusoidal PCM inputs that are representative of the signals expected in no

14、rmal operation. These are called “normal inputs“. A second group of input sequences is the set of “overload inputs“ that contain PCM signals of very large amplitudes. The third group is the set of ADPCM sequences that can exercise the algorithm in a manner that is not possible with any PCM input seq

15、uence. They test the arithmetic and algorithmic performance of the ADPCM decoder by driving it to states that are unreachable by PCM signals under normal conditions. For example, these states may result fi-om errors on the transmission line. These intermediate sequences will be denoted as “I-inputs“

16、 The values (or samples) contained in a test file are given in ASCII hexadecimal representation with two hexadecimal characters per 8-bit value. In files with 5-bit ADPCM values, the three most significant bits are set to O. Files containing 4-bit ADPCM values have the four most significant bits or

17、 each value set to O. Files that contain 3-bit ADPCM values have the five most significant bits of each word set to O. For files containing 2-bit ADPCM values, the six most significant bits are set to O. All PCM A-law inputs are in the format specified by Table 1a/G.711, i.e. the even bits are inver

18、ted. Each line in any file contains up to 32 values (or 64 characters) and ends with a line feed character. Two more hexadecimal characters representing the result of a checksum computation over the entire file are appended to each file. This checksum is the remainder of the division of 255 of the s

19、um of all sample values (two hexadecimal characters comprise a sample value) in the file. I 1 It has been noted that these diskettes do not always copy correctly using DISKCOPY due to the interaction of DISKCOPY with certain character sequences found in the test sequences. Either files should be cop

20、ied individually using COPY, or XCOPY should be used instead of DISKCOPY. Recommendation G.726 - Appendix II - Test vectors (03/91) 1 STD-ITU-T RECMN G*72b APPEND II-ENGL 1991 m qAb2591 Ob3721b bOL W S c 3 Test configurations Test sequences are derived for the two configurations shown in Figures 1 a

21、nd 2, respectively. The configuration of Figure 1 is the arrangement with the encoder transmitting to the decoder for error- free operation. The configuration of Figure 2 allows for input ADPCM words that would not normally emanate from an encoder and a PCM input word. The word formats of the variou

22、s sequences are detailed in Table 1. Encoder c Decoder , SD S b I ADPCM output sequence Decoder SD Figure 1 - Encoder and decoder configuration ADPCM input sequence PCM output sequence Name S I SD Table 1 -Word format of test sequences Description PCM input word ADPCM word PCM output word Word forma

23、t Identical to that of SP described in the sub-block COMPRESS of the synchronous coding adjuster (4.2.8/G. 72 6). As specified in the sub-block RECONST of the inverse adaptive quantizer (4.2.3/G.726). Identical to that of SP described in the sub-block COMPRESS (4.2.8G.726). 4 Test combinations The i

24、nitial state of the implementation may be either the reset state of the algorithm defined in Table 2 or a well-defined initial state that follows the application of an initialization (or homing) sequence. Accordingly, there are two types of test sequences, reset sequences and homing sequences. 2 Rec

25、ommendation G.726 - Appendix II - Test vectors (03/91) STD-ITU-T RECMN G-72b APPEND II-ENGL 1991 48b259L Ob37217 548 = Input A-law p-law A-law p-law Table 2 - State values at reset output A-law p-law p-law A-law Variable I Value O O 32 O 32 O 34 816 544 The homing sequences are based on the initial

26、states that follow the application of an initialization (homing) sequence. These initialization sequences are described in further detail in 6.4. For each initial state, both PCM laws (A-law and p-law) are considered. To allow for the interoperation of both PCM laws, four possible inputoutput combin

27、ations must be considered as shown in Table 3. Table 3 - Input/output combinations 5 Test organization Tables 4 to 7 contain the names of files containing various resethoming sequences for the following cases: 1) p-law; 2) A-law; 3) p-+A;and 4) A+. Files whose names start with an “R“ contain reset s

28、equences while the names of files for the homing sequences start with an “H“. The suffix “.I“ is reserved for the intermediate ADPCM encoder response to a PCM input. Files with the suffix “.O“ are the output PCM files. 3 Recommendation G.726 - Appendix II - Test vectors (03/91) STD-ITU-T RECMN G-72b

29、 APPEND II-ENGL 1771 = qb259L Ob372LB 4Bq output (PCM) RN16FM.0 HN16FM.O RN24FM.0 HN24FM.0 RN32FM.0 HN32FM.0 Input Output Input Intermediate (ADPCM) (PCM) (PCM) (ADPCM) I16 R116FM.0 0VR.M RV16FM.I HI 16FM.0 HVl6FM.I I24 R124FM.0 0VR.M RV24FM.I H124FM.0 HV24FM.I I32 R132FM.0 0VR.M RV32FM.I H132FM.0 H

30、V32FM.I Algorithm 16F Normal Input Intermediate Output (PCM) (ADPCM) (PCM) Ni2M.A RN16FA.I RN16FA.0 HN16FA.I HN16FA.0 RN24FA.I HN24FA.I RN24FA.0 HN24FA.0 Algorithm 16F 24F 32F Normal Input Intermediate Output Input (PCM) (ADPCM) (PCM) (PCM) NRM.M RN 16FM.I RN 16FC.0 0VR.M HN16FM.I HN16FC.0 NRM.M RN2

31、4FM.I RN24FC.0 0VR.M HN24FM.I HN24FC.0 Ni2M.M RN32FM.I RN32FC.0 0VR.M HN32FM.I HN32FC.0 Table 4 - Reset and homing sequences for p-law Algorithm i- Normal -1- i-input I Overload RV 16FM.0 HV 16FM.0 RV24FM.0 HV24FM.0 RV32FM.0 HV32FM.0 HN24FM.I NRM.M RN32FM.I I HNFM.I RN40FM.0 1140 I R140FM.0 I 0VR.M

32、1 RV40FM.I HN40FM.0 H140FM.0 HV40FM.I RV40FM. O HV40FM.0 HN40FM.I Table 5 - Reset and homing sequences for A-law I-input Overload 1 Input Output (ADP0 (PCM) RI 16FA.0 H116FA.0 R124FA.0 H124FA.0 0VR.A 24F INRM.A 0VR.A RN32FA.I HN32FA.I RN3 2 FA. O HN32FA.0 R132FA.0 132 I H132FA.0 0VR.A RN40FA.0 HN40F

33、A.0 R140FA.0 140 I H140FA.0 RN40FA.I HN40FA.I Table 6 - Reset and homing cross sequences for p + A Overload Intermediate (ADPCM) output (PCM) RV 16FM.I HV 16FM.I RV 16FC.0 HV 16FC.0 RV24FM.I HV24FM.I RV24FC.0 HV24FC.0 - RV32FM.I HV3 2FM.I RV40FM.I HV40FM.I RV32FC.0 HV32FC.0 RN40FM.I 1 RN40FC.0 1 0VR

34、M I 1 HN40FM.I HN40FC.0 40F RV40FC.0 HV40FC.0 4 Recommendation G.726 - Appendix II - Test vectors (03/91) - STD-ITU-T RECMN G.72b APPEND II-ENGL 1771 qBb2591 Ob37217 310 Input (PCM) NRh4.A Table 7 - Reset and homing cross sequences for A + p Intermediate (ADPCM) RN 16FA.I HN 16FA.I RN24FA.I HN24FA.

35、I Algorithm 16F 24F I NRM.A Normal RN32FA.I HN32FA.I 40F NRM.A RN40FA.I HN40FA.I Overload I output Input WM) (ADPCM) 1 1 RV 16FX.0 HV 16FX.O HN16FX.0 RN6FX.o I oVR.A RV24FA .I RV24FX.0 HN24FX.0 HV24FA.I HV24FX.0 HN32FX.0 HV32FA.I HV32FX.0 RV40FX.0 HN40FX.0 RN40FX.0 I OVReA HV40FX.0 5.1 Reset test se

36、quences I l The test sequences that are available when the initial state of the algorithm in the reset state are: p-law (A-law) PCM encoder input sequences for normal operation: NRh4.M and NRM.A. ADPCM encoder output sequences corresponding to the input in 1) and for the various rates: RN16FM.1, RN1

37、6FA.1, RN24FM.1, RN24FA.1, RN32FM.1, RN32FA.1, RN40FM.I and RN40FA.I. p-law (A-law) PCM decoder output sequences corresponding to the ADPCM input in 2): RN 16FM.0, RN 16FA.0, RN24FM.0, RN24FA.0, RN32FM.0, RN32FA.0, RN40FM.0 and RN40FA.0. ADPCM intermediate sequences that are applied to the decoder:

38、I16., 124, I32 and 140. p-law (A-law PCM) output sequence corresponding to the I-input ADPCM decoder input in 4): RI1 6FM.0, RI1 6FA.0, RI24FM.0, RI24FA.0, RI32FM.0, RI32FA.0, R140FM.0 and R140FA.0. y-law (A-law) PCM encoder input sequence for overload conditions: 0VR.M and 0VR.A. ADPCM encoder outp

39、ut sequence in response to the input in 6): RV16FM.1, RV16FA.1, RV24FM.1, RV24FA.1, RV32FM.1, RV32FA.1, RV40FM.I and RV40FA.I. p-law (A-law) PCM output sequence corresponding to the ADPCM encoder output in 7): RVl6FM.0, RV16FA.0, RV24FM.0, RV24FA.0, RV32FM.0, RV32FA.0, RV40FM.0 and RV40FA.0. The p +

40、 A and A -., p cross test sequences for the normal and overload cases: RN16FC.0, RV 16FC.0, RN24FC.0, RV24FC.0, RN32FC.0, RV32FC.0, RN40FC.0, RV40FC.0, RN16FX.0, RV16FX.0, RN24FX.0, RV24FX.0, RN32FX.0, RV32FX.0, RN40FX.0 and RV40FX.0. Homing test sequences The test sequences in this are: 1) Initial

41、ization (homing) sequence to drive the implementation to a known initial state: PCM-IN1T.M for the p-law and PCM-IN1T.A for the A-law. Recommendation 6.726 - Appendix II - Test vectors (03/91) 5 STD-ITU-T RECMN G-726 APPEND II-ENGL 1991 W 48b2571 Ob37220 032 m 2) 3) 4) p-law (A-law) PCM encoder inpu

42、t sequence for normal operation starting from this normal state: NRM.M and NRM.A. ADPCM encoder output sequence corresponding to the input in 2): HN16FM.1, HN16FA.1, HN24FM.1, HN24FA.1, HN32FM.1, HN32FA.1, HN40FM.I and HN40FA.I. p-law (A-law) PCM decoder output sequence corresponding to the ADPCM en

43、coder output in 3): HN16FM.0, HN16FA.0, HN24FM.0, HN24FA.0, HN32FM.0, HN32FA.0, HN40FM.0 and HN40FA.0. 5) ADPCM initialization sequence for I-input operation: I-INI_lG.M, I-INI-24.M, I-INI-32.M, and I-INI40.M for p-law; I-INI-16.A, I-INI-24.A, I - IN1 32.A and I-INI40.A for A-law. p-law (A-law PCM)

44、output sequence corresponding to the I-input ADPCM decoder input in 5): HI16FM.0, HIl6FA.0, HI24FM.0, HI24FA.0, HI32FM.0, HI32FA.0, H140FM.0 and HI40FA.O. 7) p-law (A-law) PCM encoder input sequence for overload conditions: 0VR.M and 0VR.A. 8) ADPCM encoder output sequence corresponding to the input

45、 in 7): HV16FM.0, HV16FA.0, HV24FM.0, HV24FA.0, HV32FM.0, HV32FA.0, HV40FM.0 and HV40FA.0. p-law (A-law) PCM output sequence corresponding to the ADPCM sequence in 8): HV16FM.0, HV16FA.0, HV24FM.0, HV24FA.0, HV32FM.0, HV32FA.0, HV40FM.0 and HV40FA.0. The p + A and A -, p cross test sequences for the

46、 normal and overload cases: HN16FC.0, HV1 6FC.0, HN24FC.0, HV24FC.0, HN32FC.0, HV32FC.0, HN40FC.0, HV40FC.0, HN16FX.0, HVlGFX.0, HN24FX.0, HV24FX.0, HN32FX.0, HV32FX.0, HN40FX.0, and HV40FX.0. 6) 9) 10) 6 Description of the input sequences 6.1 PCM normal input The PCM normal input sequences consist

47、of 16 384 values that represent narrow-band and broadband signal sequences as detailed in Table 8. NRM.M is the PCM normal p-law input sequence while NRM.A is the corresponding A-law input sequence. 6 Recommendation G.726 - Appendix II - Test vectors (03/91) STD-ITU-T RECMN G*72b APPEND II-ENGL 1991

48、 9 48b2591 Ob37221 T77 9 Table 8 - Sequence of PCM test signal I Signal I Length 3504 Hz tone 2054 Hz tone 1504 Hz tone 504 Hz tone 254 Hz tone 1254 Hz tone 2254 Hz tone 3254 Hz tone 4000 Hz tone DC, positive, low level DC, value of zero DC, negative, low level 4800 bids differential phase shift key

49、ed voice-band data switched carrier 4800 bids differential phase shift keyed voice-band data continuous carrier (with asynchronous switched carrier secondary channel) I Total length of sequence I 1 024 1 024 1 024 1 024 1024 1 024 024 i 5 12 1024 i 5 12 5 12 5 12 16384 I 6.2 PCM overload input The PCM overload input sequences have 2048 values from three high level ( +1 dBmO) single frequency tones at 404, 1004 and 3204 Hz arranged in various combinations and for differing intervals. The sequence is generated digitally without analogue filtering but w