1、INTERNATIONAL TELECOMMUNICATION UNION)45G134 6 G0BISTELECOMMUNICATIONSTANDARDIZATION SECTOROF ITU$!4!G0G0#/-5.)#!4)/./6%2G0G04(%G0G04%,%0(/.%G0G0.%47/2+G0“)43G0G00%2G0G03%#/.$G0G0-/$%-G0G07)4(!54/-!4)#G0G0%15!,):%2G0G034!.$!2$):%$amended at Geneva, 1980,Malaga-Torremolinos, 1984)IntroductionThis mod
2、em is intended to be used over any general leased circuits not necessarily conforming toRecommendation M.1020 1. A provision for a fast start-up sequence is made to allow the use of this modem formultipoint polling applications if the circuits used conform to Recommendation M.1020.On leased circuits
3、, considering that there exist and will come into being many modems with features designedto meet the requirements of the Administrations and users, this Recommendation in no way restricts the use of any othermodems. This Recommendation does not eliminate the need for manually equalized modems accor
4、ding toRecommendation V.27 or application of other automatically equalized 4800 bits per second modems.The provisions of this Recommendation are to be regarded as provisional in order to provide service where it isurgently required and between locations where it is expected that a reasonably satisfa
5、ctory service can be given.1 Principal characteristicsThe principal characteristics for this recommended modem are very similar to the characteristics of a modemconforming to Recommendation V.27 with the exception of the equalizer used and these characteristics are as follows:a) operates in a full-d
6、uplex or half-duplex mode over 4-wire leased circuits or in a half-duplex mode over2-wire leased circuits;b) at 4800 bits per second operation, modulation is 8-phase differentially encoded as described inRecommendation V.27;c) reduced rate capability at 2400 bits per second with 4-phase differential
7、ly encoded modulation scheme asdescribed in Recommendation V.26, Alternative A;d) possibility of a backward (supervisory) channel at modulation rates up to 75 bauds in each direction oftransmission, the provision and the use of these channels being optional;e) inclusion of an automatic adaptive equa
8、lizer with a specific start-up sequence for RecommendationM.1020 1 lines and an alternate start-up sequence for much lower grade lines.2 Line signals at 4800 and 2400 bits per second operation2.1 Carrier frequencyThe carrier frequency is to be 1800 1 Hz. No separate pilot tones are provided. The pow
9、er levels used willconform to Recommendation V.2.2.1.1 Spectrum at 4800 bits per secondA 50% raised cosine energy spectrum shaping is equally divided between the receiver and transmitter. Theenergy density at 1000 Hz and 2600 Hz shall be attenuated 3.0 dB 2.0 dB with respect to the maximum energy de
10、nsitybetween 1000 Hz and 2600 Hz.2.1.2 Spectrum at 2400 bits per secondA minimum of 50% raised cosine energy spectrum shaping is equally divided between the receiver andtransmitter. The energy density at 1200 Hz and 2400 Hz shall be attenuated 3.0 dB 2.0 dB with respect to themaximum energy density
11、between 1200 Hz and 2400 Hz.2 Fascicle VIII.1 - Rec. V.27 bis2.2 Division of power between the forward and backward channelIf simultaneous transmission of the forward and backward channels occurs in the same direction, a backwardchannel should be 6 dB lower in power level than the forward (data) cha
12、nnel.2.3 Operation at 4800 bits per second2.3.1 Data signalling and modulation rateThe data signalling rate shall be 4800 bits per second 0.01%, i.e. the modulation rate is 1600 bauds 0.01%.2.3.2 Encoding data bitsThe data stream to be transmitted is divided into groups of three consecutive bits (tr
13、ibits). Each tribit is encodedas a phase change relative to the phase of the preceding signal element (see Table 1/V.27 bis). At the receiver, the tribitsare decoded and the bits are reassembled in correct order. The left-hand digit of the tribit is the one occurring first in thedata stream as it en
14、ters the modulator portion of the modem after the scrambler.TABLE 1/V.27 bisTribit valuesPhase change(see Note)00001111001111001001100104590135180225270315Note - The phase change is the actual on-line phase shift in thetransition region from the centre of one signalling element to thecentre of the f
15、ollowing signalling element.2.4 Operation at 2400 bits per second2.4.1 Data signalling and modulation rateThe data signalling rate shall be 2400 bits per second 0.01%, i.e. the modulation rate is 1200 bauds 0.01%.2.4.2 Encoding data bitsAt 2400 bits per second the data stream is divided into groups
16、of two bits (dibits). Each dibit is encoded as aphase change relative to the phase of the immediately preceding signal element (see Table 2/V.27 bis). At the receiver,the dibits are decoded and reassembled in the correct order. The left-hand digit of the dibit is the one occurring first inthe data s
17、tream as it enters the modulator portion of the modem after the scrambler.Fascicle VIII.1 - Rec. V.27 bis 3TABLE 2/V.27 bisDibit values Phase change (see Note)00011110090180270Note - The phase change is the actual on-line phase shift in thetransition region from the centre of one signalling element
18、to thecentre of the following signalling element.2.5 Operating sequences2.5.1 Turn-ON sequenceDuring the interval between the OFF to ON transition of circuit 105 and the OFF to ON transition of circuit106, synchronizing signals for proper conditioning of the receiving modem must be generated by the
19、transmittingmodem. These are signals to establish carrier detection, AGC if required, timing synchronization, equalizer convergenceand descrambler synchronization.Two sequences are defined, i.e.:a) a short one for 4-wire circuits conforming to Recommendation M.1020 1 operation,b) a long one for 4-wi
20、re circuits which are much worse than Recommendation M.1020 1 and for 2-wirecircuits.The sequences, for both data rates, are divided into three segments as in Table 3/V.27 bis.TABLE 3/V.27 bisSegment 1 Segment 2 Segment 3 Total of Segments 1, 2 and 3Type of line signalContinuous 180phase reversals0-
21、180 2-phaseequalizerContinuousscrambledTotal “Turn-ON“sequence timeconditioningpatternONEs4800 bit/s 2400 bit/sNumber of symbolintervals (SI) a)a) 14 SIb) 50 SIa) 58 SIb) 1074 SI8 SIa) 50 msb) 708 msa) 67 msb) 943 msa) SI = symbol intervals. The durations of Segments 1, 2 and 3 are expressed in numb
22、er of symbol intervals, these numbersbeign the same in fallback operation.2.5.1.1 The composition of Segment 1 is continuous 180 phase reversals on line for 14 symbol intervals in the case ofsequence a), for 50 symbol intervals in the case of sequence b).2.5.1.2 Segment 2 is composed of an equalizer
23、 conditioning pattern which is derived from a pseudo-random sequencegenerated by the polynomial:1 + x -6+ x -72.5.1.2.1 For operation at 4800 bit/s the equalizer conditioning pattern is derived by using every third bit of the pseudo-random sequence defined in 2.5.1.2. When the derived pattern contai
24、ns a ZERO, 0 phase change is transmitted; when4 Fascicle VIII.1 - Rec. V.27 bisit contains a ONE, 180 phase change is transmitted. Segment 2 begins with 0, 180, 180, 180, 180, 180, 0, . . .according to the derived pattern and continues for 58 symbol intervals in the case of sequence a) and for 1074
25、symbolintervals in the case of sequence b). An example of the detailed sequence generation is described in Appendix I.2.5.1.2.2 On leased circuits, considering that there exist modems which comply with 2.5.1.2.1 at 4800 bit/s, but whichdiffer in their “Turn-ON“ sequences at 2400 bit/s, the following
26、 alternative equalizer conditioning patterns are defined:i) In the first alternative, the equalizer conditioning pattern is identical to that defined in 2.5.1.2.1.ii) In the second alternative, the equalizer conditioning pattern is derived by using every second bit of thepseudo-random pattern define
27、d in 2.5.1.2. When the derived sequence contains a ZERO, 0 phasechange is transmitted; when it contains a ONE, 180 phase change is transmitted. Segment 2 begins with0, 180, 0, 180, 180, 0, 180, . . . according to the derived pattern and continues for 58 symbolintervals in the case of sequence a) and
28、 for 1074 symbol intervals in the case of sequence b).2.5.1.3 Segment 3 commences transmission according to the encoding described in 2.3 and 2.4 above withcontinuous data ONEs applied to the input of the data scrambler. Segment 3 is 8 symbol intervals. At the end of Segment3, circuit 106 is turned
29、ON and user data are applied to the input of the data scrambler.2.5.1.4 The phase change sequences for Segments 2 and 3 for 4800 bit/s and 2400 bit/s are shown in Table 4/V.27 bis.TABLE 4/V.27 bis a)Data speed Segment 2 Segment 34800 bit/s Phase changePRSb)00111801011801011801001801001801010001. . .
30、 . . . . . . . . . . .180110180100001000012701002251103151019001045000450001801111801112400 bit/salternative i)Phase changePRS b)00111801011801011801001801001801010001. . . . . . . . . . . . .18011018010000100001270109001270102701027010270100000002400 bit/salternative ii)Phase changePRSb)00118011001
31、180101801100018010180. . . 100001801018010180110000009001900118011270100001801127010Duration 58 or 1074 symbol intervals (Beginning and ending PRS and symbol sequencesare the same for both durations) 8 symbol intervals a)For a description of how the alternative sequences for Segments 2 and 3 may be
32、generated, refer to the Note at the end of Appendix I.b)PRS is the pseudo-random sequence defined in 2.5.1.2. The underlined bits determine the phase changes.Fascicle VIII.1 - Rec. V.27 bis 52.5.2 Turn-OFF sequenceThe line signal emitted after the ON to OFF transition of circuit 105 is divided into
33、two segments as shown inTable 5/V.27 bis.TABLE 5/V.27 bisSegment A Segment B Total of SegmentsA and BType of line signalRemaining datafollowed by continuousscrambled ONEsNo transmitted energyTotal“Turn-OFF“ timeDuration 5 to 10 ms 20 ms 25 to 30 msIf an OFF to ON transition of circuit 105 occurs dur
34、ing the Turn-OFF sequence, it will not be taken intoaccount until the end of the Turn-OFF sequence.In addition, in the case of half-duplex operation on two wires, if circuit 105 goes ON during the reception of theSegment A of the Turn-OFF sequence, optionally the transmission of the Turn-ON sequence
35、 shall be started within atime period of less than 20 ms after the end of reception of Segment A.3 Received signal frequency toleranceNoting that the carrier frequency tolerance allowance of the transmitter is 1 Hz and assuming a maximumdrift of 6 Hz in the connection between the modems, then the re
36、ceiver must be able to accept errors of at least 7 Hzin the received frequencies.4 Backward channelThe modulation rate, characteristic frequencies, tolerances, etc. to be as recommended for the backward channelin Recommendation V.23. This does not preclude the use of a higher speed backward channel
37、with operationalcapability of 75 bauds or higher, bearing the same characteristic frequencies as the V.23 backward channel.5 Interchange circuits5.1 List of essential interchange circuits (Table 6/V.27 bis)5.2 Response times of circuits 106, 109, 121 and 122 (Table 7/V.27 bis)5.2.1 Circuit 109Circui
38、t 109 must turn ON after synchronizing is completed and prior to user data appearing on circuit 104.5.2.2 Circuit 106Circuit 106 response times are from the connection of an ON or OFF condition on circuit 105 to the appearanceof the corresponding ON or OFF condition on circuit 106.6 Fascicle VIII.1
39、- Rec. V.27 bisTABLE 6/V.27 bisInterchange circuitForward (data) channelhalf-duplex of full-duplex(see Note)No. DesignationWithoutbackwardchannelWith backwardchannel102103104105106107108/1109111113114115118119120121122Signal ground or common return .Transmitted data .Received data .Request to send .
40、Ready for sending Data set ready Connect data set to line Data channel received line signal detector Data signal rate selector (DTE source) Transmitter signal element timing(DTE source) Receiver signal element timing(DCE source) Receiver signal element timing(DCE source) Transmitter backward channel
41、 data .Received backward channel data .Transmit backward channel line signal .Backward channel ready .Backward channel received line signal detector .XXXXXXXXXXXXXXXXXXXXXXXXXXXXXNote - All essential interchange circuits and any others which are provided shall comply with the functional andoperation
42、al requirements of Recommendation V.24. All interchange circuits indicated by X shall be properly terminated inthe data terminal equipment and in the data circuit-terminating equipment in accordance with the appropriateRecommendation for electrical characteristics (see 6).Fascicle VIII.1 - Rec. V.27
43、 bis 7TABLE 7/V.27 bisResponse timesCircuit 106 4800 bits per second 2400 bits per secondOFF to ON a) 25 msb) 708 msa) 67 msb) 944 msON to OFF 2 msCircuit 109OFF to ON See 5.2.1ON to OFF 5 to 15 msCircuit 121OFF to ON 80 to 160 msON to OFF 2 msCircuit 122OFF to ON 80 msON to OFF 15 to 80 msNote - a)
44、 and b) refer to sequence a) and sequence b) as defined in 2.5.1.5.3 Threshold of data channel and backward channel received line signal detectorsLevels of received line signal at receiver line terminals:For use over ordinary quality leased circuits (ref. Recommendation M.1040 2)Threshold for circui
45、ts 109/122:- greater than -43 dBm: OFF to ON- less than -48 dBm: ON to OFF- For use over special quality leased circuits (ref. Recommendation M.1020 1)Threshold for circuit 109:- greater than - 26 dBm: OFF to ON- less than -31 dBm: ON to OFFThreshold for circuit 122:- greater than - 34 dBm: OFF to O
46、N- less than -39 dBm: ON to OFFThe condition of circuits 109 and 122 for levels between the above levels is not specified except that the signaldetectors shall exhibit a hysteresis action such that the level at which the OFF to ON transition occurs is at least 2 dBgreater than that for the ON to OFF
47、 transition.8 Fascicle VIII.1 - Rec. V.27 bis5.4 Clamping in half-duplex modeThe DCE, when operating in half-duplex mode on a 2-wire line, shall hold, where implemented:a) circuit 104 in the binary 1 condition and circuit 109 in the OFF condition when circuit 105 is in theON condition and, where req
48、uired to protect circuit 104 from false signals, for a period of150 25 ms following the ON to OFF transition on circuit 105; the use of this additional delay isoptional, based on system considerations;b) circuit 119 in the binary 1 condition and circuit 122 in the OFF condition when circuit 120 is i
49、n theON condition and, where required to protect circuit 119 from false signals, for a time intervalfollowing the ON to OFF transition on circuit 120. The specific duration of this time interval is leftfor further study. The additional delay is optional, based on system considerations.5.5 Fault condition of interchange circuits(See Recommendation V.28, 7 for association of the receiver failure detection types.
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