1、INTERNATIONAL TELECOMMUNICATION UNION)45G134 6 TELECOMMUNICATIONSTANDARDIZATION SECTOROF ITU$!4!G0G0#/-5.)#!4)/./6%2G0G04(%G0G04%,%0(/.%G0G0.%47/2+G0 G0“)43G0G00%2G0G03%#/.$G0G0-/$%-34!.$!2$):%$G0G0b) capable of operating in a duplex mode with continuous carrier;c) combined amplitude and phase modul
2、ation with synchronous mode of operation;d) inclusion of an eight state trellis coded modulation;e) optional inclusion of a multiplexer for combining data rates of 12 000, 9600, 7200, 4800 and 2400 bits persecond (see Note 3).Note 1 - The principal use of this recommended modem is on 4-wire leased c
3、ircuits. Other applications, such asstand-by operation on the switched telephone network, half duplex or multipoint operation are for further study. Circuitsshould be of the special quality type, e.g. M.1020 1 or M.1025 2. However, administrations and users may wish tonote that modems conforming to
4、this Recommendation, even assuming proper implementations, will not necessarilyoperate satisfactorily on all circuits conforming to M.1020 and M.1025; particularly where noise is at or near thespecified limiting magnitude.Note 2 - Attention should be given to the selection of appropriate equalizatio
5、n techniques in the modemimplementation, if acceptable performance on circuits conforming to Recommendation M.1025 is desired.Note 3 - When the multiplexer option is installed, provisions in section 10 may supersede provisions given inother sections.2 Line signals2.1 The carrier frequency is to be 1
6、800 1 Hz. The power levels used will conform to Recommendation V.2.2.2 Signal space coding2.2.1 At 14 400 bits per second, the scrambled data stream to be transmitted is divided into groups of sixconsecutive data bits. As shown in Figure 1/V.33, the first two bits in time Qln, and Q2nin each group,
7、are firstdifferentially encoded into Yl and Y2 according to Table 1A/V.33. The two differentially encoded bits Ylnand Y2nareused as input to a systematic convolutional encoder which generates a redundant bit Y0n. This redundant bit and the sixinformation-carrying bits Yln, Y2n, Q3n, Q4n, Q5n, and Q6
8、nare then mapped into the coordinates of the signal elementto be transmitted according to the signal space diagram shown in Figure 2/V.33.2.2.2 At the fallback rate of 12 000 bit/s, the scrambled data stream to be transmitted is divided into groups of fiveconsecutive data bits. The trellis coding sc
9、heme shown in Figure 1/V.33, is used with the modification that first, the linedesignated by Q6nis removed and second, the signal element mapping is now as shown in Figure 3/V.33.2.2.3 Table 1 B/V.33 describes the differential encoding used for the 4800 bit/s rate signal in segment 3 ofsynchronizing
10、 signals ( 8.3).2 Fascicle VIII.1 - Rec. V.33TABLE 1A/V.33Differential encoding for use with trellis codingInputs Previous outputs OutputsQ1nQ2nY1n-1Y2n-2Y1nY2n000000001111111100001111000011110011001100110011010101010101010100110011110011000101101001101001TABLE 1B/V.33Differential quadrant coding fo
11、r 4800 bit/s rate signalInputs Previous outputs Phase quadrant Outputs Signal element for CoordinatesQ1nQ2nY1n-1Y2n-1Y1nY2n4800 bit/s Re Im0000000000110101+90 01011100DACB-2-6+6+2+6-2+2-600001111001101010 00110101CDBA+6-2+2-6+2+6-6-21111000000110101+180 11001010ABDC-6+2-2+6-2-6+6+21111111100110101+2
12、70 10100011BCAD+2+6-6-2-6+2-2+6Note - Q1 is the first bit in time.Fascicle VIII.1 - Rec. V.33 3Note - See Figure 2/V.33 for 14 400 bit/s rate, Figure 3/V.33 for 12 000 bit/s.FIGURE 1/V.33Trellis coder at 14 400 bit/s and 12 000 bit/s4 Fascicle VIII.1 - Rec. V.33Binary numbers refer to Q6n, Q5n, Q4n,
13、 Q3n, Y2n, Yln, Y0n,A, B , C, D refer to synchronizing signal elementsFIGURE 2/V.33Signal space diagram and mapping for trellis-coded modulation at 14 400 bit/sFascicle VIII.1 - Rec. V.33 5Binary numbers refer to Q5n, Q4n, Q3n, Y2n, Yln, Y0n,A, B , C, D refer to synchronizing signal elementsFIGURE 3
14、/V.33Signal space diagram and mapping for trellis-coded modulation at 12 000 bit/s3 Data signalling and modulation ratesThe data signalling rates shall be 14 400 and 12 000 bit/s 0.01%. The modulation rate is 2400 bauds 0.01%.4 Received signal frequency toleranceThe carrier frequency tolerance allow
15、ance at the transmitter is 1 Hz. Assuming a maximum frequency drift of 6 Hz in the connection between the modems, then the receiver must be able to accept errors of at least 7 Hz in thereceived signal frequency.6 Fascicle VIII.1 - Rec. V.335 Interchange circuits5.1 List of interchange circuits (Tabl
16、e 2/V.33)TABLE 2/V.33Interchange circuit (see Note 1)No. Designation Notes102103104105106107109111112113114115140141142Signal ground or common returnTransmitted dataReceived dataRequest to sendReady for sendingData set readyData channel received line signal detectorData signalling rate selector (DTE
17、 source)Data signalling rate selector (DCE source)Transmitter signal element timing (DTE source)Transmitter signal timing (DCE source)Receiver signal element timing (DCE source)Loopback/Maintenance testLocal loopbackTest indicatorNote 2Note 3Note 3Note 1 - All essential interchange circuits and any
18、others which are provided shall comply with the functional and operationalrequirements of Recommendation V.24. All interchange circuits provided shall be properly terminated in the data terminal equipmentand in the data circuit-terminating equipment in accordance with the appropriate Recommendation
19、for electrical characteristics (see 6).Note 2 - Not essential for continuous carrier operation.Note 3 - Interchange circuits 140 and 141 are optional.5.2 Threshold and response times of circuit 1095.2.1 Threshold- greater than -26 dBm: circuit 109 ON- less than - 33 dBm: circuit 109 OFFThe condition
20、 of circuit 109 for levels between -26 dBm and -33 dBm is not specified except that the signaldetector shall exhibit a hysteresis action, such that the level at which the OFF to ON transition occurs is at least 2 dBgreater than that for the ON to OFF transition.5.2.2. Response times- ON to OFF: 40 1
21、0 ms:- OFF to ON:1) for initial equalization, circuit 109 must be ON prior to user data appearing on circuit 104;2) for re-equalization during data transfer, circuit 109 will be maintained in the ON condition; duringthis period, circuit 104 may be clamped to the binary 1 condition;Fascicle VIII.1 -
22、Rec. V.33 73) after a line signal interruption that lasts more than the ON to OFF response time:a) when no new equalization is needed, 25 10 ms;b) when a new equalization is needed, circuit 109 must be ON prior to user data appearing oncircuit 104.Response times of circuit 109 are the times that ela
23、pse between the connection or removal of a line signal,generated by applying binary one to circuit 103, to or from the modem receive line terminals and the appearance of thecorresponding ON or OFF condition on circuit 109.Note - Circuit 109 ON to OFF response time should be suitably chosen within th
24、e specified limits to ensure thatall valid data bits have appeared on circuit 104.5.3 Response time for circuit 106Following the complete training procedure, the time between the OFF to ON transition of circuit 105 and theOFF to ON transition of circuit 106 shall be 15 ms 5 ms.The time between the O
25、N to OFF transition of circuit 105 and the ON to OFF transition of circuit 106 shall besuitably chosen to ensure that all valid signal elements have been transmitted.6 Electrical characteristics of interchange circuits6.1 Use of electrical characteristics conforming to Recommendation V.28 is recomme
26、nded together with theconnector pin assignment plan specified by ISO 2110 3.6.2 Fault condition on interchange circuits(See 7 of Recommendation V.28 for association of the receiver failure detection types).6.2.1 The DTE should interpret a fault condition on circuit 107 as an OFF condition using fail
27、ure detection type 1.6.2.2 The DCE should interpret a fault condition on circuit 105 as an OFF condition using failure detection type 1.6.2.3 All other circuits not referred to above may use failure detection types 0 or 1.6.3 Timing arrangements8 Fascicle VIII.1 - Rec. V.33Clocks shall be included i
28、n the modem to provide the data terminal equipment with transmitter signal elementtiming, circuit 114, and receiver signal element timing, circuit 115. In this arrangement, the transmitter may either run asan independent timing source or with loopback timing (transmit timing slaved to receive timing
29、). Loopback timing maybe desirable in some network applications.Alternatively, the transmitter signal element timing may be originated in the data terminal equipment and betransferred to the modem via interchange circuit 113.7 ScramblerA self-synchronizing scrambler/descrambler having the generating
30、 polynomial 1 + x-18+ x-23, shall be includedin the modem.At the transmitter the scrambler shall effectively divide the message polynomial, of which the input datasequence represents the coefficients in descending order, by the scrambler generating polynomial to generate thetransmitted sequence. At
31、the receiver the received polynomial, of which the received data sequence represents thecoefficients in descending order, shall be multiplied by the scrambler generating polynomial to recover the messagesequence.The detailed scrambling and descrambling processes are described in the Annex.8 Synchron
32、izing signalsTransmission of synchronizing signals may be initiated by the modem. When the receiving modem requiresresynchronizing, it shall turn circuit 106 OFF and generate a synchronizing signal sequence.Fascicle VIII.1 - Rec. V.33 9The synchronizing signals for all data signalling rates are divi
33、ded into four segments as in Table 3/V.33.TABLE 3/V.33Segment 1Segment 2TRNSegment 3 Segment 4 TotalType of line signal AlternationsABABEqualizerconditionpatternRate sequence Scrambled allbinaryONEsTotalsynchronizingsignal timeNumber of symbolintervals256 2976 64 48 3344Approximate time inms106 1240
34、 27 20 13938.1 Segment 1 consists of alternations between states A and B as shown in Figures 2 and 3/V.33 for a duration of256 symbol intervals.8.2 Segment 2: Equalizer conditioning patternThe segment consists of the sequential transmission of four signal elements A, B, C and D. These signalelements
35、 are shown in Figures 2/V.33 and 3/V.33. The equalizer conditioning pattern is a pseudo-random sequence at4800 bit/s generated by the 1 + x-18+ x-23data scrambler. During segment 2 any differential quadrant encoding isdisabled and the scrambled dibits are encoded as follows:00 = C 01 = D 11 = A 10 =
36、 BWith a binary 1 applied to the input, the initial state of the scrambler shall be selected to produce the followingscrambler output pattern and corresponding signal elements:00 01 00 01 00 01 00 01 00 01 00 01 10 01 10 01C D C D C D C D C D C D B D B DSegment 2 continues for 2976 symbol intervals.
37、8.3 Segment 3: Rate signalThe rate signal consists of a 16-bit binary sequence repeated 8 times. The sequence is defined in Table 4/V.33,scrambled and transmitted at 4800 bit/s with dibits differentially encoded as in Table 1B/V.33. The differential encodershall be initialized using the final symbol
38、 of the previous segment.The first two bits and subsequent dibits of each rate sequence shall be encoded as one signal state.The rate signal may be used for establishing the data signalling rate between the modems, and providinginformation regarding multiplexer configuration, or other configuration
39、information (subject to further study). WhenB14 = 0, only data signalling rate information is conveyed according to Table 4A/V.33. When B14 = 1, the bitassignment of Table 4B/V.33 applies.The minimum requirement for detection is the receipt of two consecutive identical 16-bit sequences each withbits
40、 B0-3, B7, Bll and B15 conforming with Table 4/V.33. Following the detection of the rate sequence, the receivershall be conditioned to receive data at the highest common rate with the indicated multiplexer configuration.10 Fascicle VIII.1 - Rec. V.33TABLE 4A/V.33Bit designations0 1 2 3 4 5 6 7 8 9 1
41、0 11 12 13 14 150000 1 1 01B0-3, B7, B11, B15 For synchronizing on a received rate signalB4-6 Not yet defined (for further study)B8 1 Denotes ability to transmit and receive data at 12 000 bit/s (Note)B9 1 Denotes ability to transmit and receive data at 14 000 bit/s (Note)B10, B12, B13 Not yet defin
42、ed (for further study)Note - When transmitting a rate signal, the modern will transmit bits B8 B9 equal to 11 or 01 when the data signallingrate of segment 4 equals 14.4 kbit/s and B8 B9 = 10 when the data signalling rate of segment 4 equals 12 kbit/s.TABLE 4B/V.33Bit designations0 1 2 3 4 5 6 7 8 9
43、 10 11 12 13 14 150000 1 1 01B0-3, B7, B11, B15 For synchronzing on a received rate signalB4, B5 00 Denotes that B6, B10, B12, B13 define multiplexer configuration select(Note 1)B8 1 Denotes ability to transmit and receive data at 12 000 bit/s (Notes 1 and 3)B9 1 Denotes ability to transmit and rece
44、ive data at 14 000 bit/s (Notes 1 and 3 )B6, B10, B12, B13 Multiplexer configuration select (see Note 2 and Tables 5A, 5B/V.33)Note 1 - Other combinations of B4, B5 may be used to denote that B6, B8, B9, B10, B12 and B13 define otherconfiguration information (for further study).Note 2 - a) B6, B10,
45、B12, B13 = all ZEROs: Manual Mode;b) B6, B10, B12, B13 Binary representation of 1 through 11 (B6 = MSB, most significant bit) denotes desired multiplexer configuration as shown in Tables 5A and 5B/V.33;c) B6, B10, B12, B13 = all ONEs: Remotely Programmable Mode. If a modem is so configured it will a
46、lways transmit this pattern.d) B6, B10, B12, B13 The unused combinations are available for use as manufacturers option;e) It is recommended that either both modems be configured with the identical multiplexer Mode or one modem be configured in the remotely programmable multiplexer Mode.Note 3 - When
47、 transmitting a rate signal, the modems will transmit bits B8 B9 equal to 11 or 01 when the data signalling rateof segment 4 equals 14.4 kbit/s and B8 B9 = 10 when the data signalling rate of segment 4 equals 12 kbit/s.Fascicle VIII.1 - Rec. V.33 118.4 Segment 4The differential encoding to be used d
48、uring this segment is defined in Table 1A/V.33. The differential encodershall be initialized using the first symbol of the previous segment. Segment 4 shall begin with the initial states of thedelay elements of the convolutional encoder shown in Figure 1/V.33 set to zero.This segment initiates trans
49、mission at the highest rate indicated by segment 3 according to the encodingdescribed in 2.2 above with continuous binary ONEs applied to the input of the data scrambler. The duration ofsegment 4 is 48 symbol intervals. At the end of segment 4, circuit 106 is turned ON and user data are applied to the inputof the data scrambler.9 Training-retraining procedureAn automatic adaptive equalizer shall be provided in the receiver.The receiver shall incorporate a means o
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