JEDEC J-STD-020E-2014 Moisture Reflow Sensitivity Classification for Nonhermetic Surface Mount Devices.pdf

1、 JOINT INDUSTRY STANDARD Moisture/Reflow Sensitivity Classification for Nonhermetic Surface Mount Devices IPC/JEDEC J-STD-020E December 2014 Supersedes IPC/JEDEC J-STD-020D.1 March 2008 Notice IPC and JEDEC Standards and Publications are designed to serve the public interest through eliminating misu

2、nderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence of such Standards and Publications shall not in any respect

3、 preclude any member or nonmember of IPC or JEDEC from manufacturing or selling products not conforming to such Standards and Publications, nor shall the existence of such Standards and Publications preclude their voluntary use by those other than IPC or JEDEC members, whether the standard is to be

4、used either domestically or internationally. Recommended Standards and Publications are adopted by IPC or JEDEC without regard to whether their adoption may involve patents on articles, materials, or processes. By such action, IPC or JEDEC do not assume any liability to any patent owner, nor do they

5、 assume any obligation whatever to parties adopting the Recommended Standard or Publication. Users are also wholly responsible for protecting themselves against all claims of liabilities for patent infringement. The material in this joint standard was developed by the IPC Plastic Chip Carrier Cracki

6、ng Task Group (B-10a) and the JEDEC JC-14.1 Committee on Reliability Test Methods for Packaged Devices Please use the Standard Improvement Form shown at the end of this document. Copyright 2014. JEDEC Solid State Technology Association, Arlington, Virginia, and IPC, Bannockburn, Illinois, USA. All r

7、ights reserved under both international and Pan-American copyright conventions. Any copying, scanning or other reproduction of these materials without the prior written consent of the copyright holder is strictly prohibited and constitutes infringement under the Copyright Law of the United States. F

8、or Technical Information Contact: JEDEC IPC Solid State Technology Association 3000 Lakeside Drive, Suite 309S 3103 North 10th Street, Suite 240-S Bannockburn, Illinois Arlington, VA 22201-2107 60015-1249 Tel 703 907.0026 Tel 847 615.7100 Fax 703.907.7501 Fax 847.615.7105 . Supersedes: IPC/JEDEC J-S

9、TD-020D.1 March 2008 IPC/JEDEC J-STD-020D August 2007 IPC/JEDEC J-STD-020C July 2004 IPC/JEDEC J-STD-020B July 2002 IPC/JEDEC J-STD-020A April 1999 J-STD-020 -October 1996 JEDEC JESD22-A112 IPC-SM-786A -January 1995 IPC-SM-786 -December 1990 IPC/JEDEC J-STD-020E Moisture/Reflow Sensitivity Classific

10、ation for Nonhermetic Surface Mount Devices A joint standard developed by the IPC Plastic Chip Carrier Cracking Task Group (B-10a) and the JEDEC JC-14.1 Committee on Reliability Test Methods for Packaged Devices Users of this standard are encouraged to participate in the development of future revisi

11、ons. Contact: JEDEC Solid State Technology Association3103 North 10th Street, Suite 240S Arlington, VA 22201- 2107 Tel 703 907.0026 Fax 703 907.7501 IPC 3000 Lakeside Drive, Suite 309S Bannockburn, Illinois 60015-1249 Tel 847 615.7100 Fax 847 615.7105 This Page Intentionally Left BlankAcknowledgment

12、Members of the IPC Association Connecting Electronics Industries IPC Plastic Chip Carrier Cracking Task Group (B-10a)and the JEDEC Solid State Technology Association JEDEC JC-14.1 Committee on Reliability Test Methods for PackagedDevices have worked together to develop this document. We would like t

13、o thank them for their dedication to this effort.Any document involving a complex technology draws material from a vast number of sources across many continents. Whilethe principal members of the Joint Moisture Classification Working Group are shown below, it is not possible to include allof those w

14、ho assisted in the evolution of this standard. To each of them, the members of the IPC and JEDEC extend theirgratitude.IPC Plastic Chip CarrierCracking Task GroupChairSteven R. MartellSonoscan, Inc.JEDEC JC 14.1CommitteeChairIfe HsuIntel CorporationVice ChairGautam VermaAltera CorporationJoint Moist

15、ure Classification Working Group MembersDoug Derry, AccuAssemblyDavid Gaydos, ACI Technologies,Inc.Russell Nowland, Alcatel-LucentBradley Smith, Allegro MicroSystemsInc.Maurice Brodeur, Analog DevicesInc.Bill Strachan, ASTA - PortsmouthUniversityLyle Burhenn, BAE SystemsPlatform SolutionsThomas Clee

16、re, BAE SystemsPlatform SolutionsJoseph Kane, BAE Systems PlatformSolutionsMary Bellon, Boeing Research then the total time of the interruption should be excludedfrom the bake time. The interruption time should be accounted and no greater than 1 hour, then re-incorporated to ensureminimum of 24 hour

17、s. For instance, if the interruption was 45 minute, then the total bake test time would be 24 hours and45 minutes. If greater than 1 hour the bake should be restarted for a full 24 hours.5.5 Moisture Soak Place devices in a clean, dry, shallow container so that the package bodies do not touch or ove

18、rlapeach other. Submit each sample to the appropriate soak requirements shown in Table 5-1. At all times parts should behandled using proper ESD procedures in accordance with JESD625.IPC/JEDEC J-STD-020E January 201565.6 Reflow Not sooner than 15 minutes and not longer than 4 hours after removal fro

19、m the temperature/humidity cham-ber, subject the sample to 3 cycles of the appropriate reflow conditions as defined in Table 5-2 and Figure 5-1. If the tim-ing between removal from the temperature/humidity chamber and initial reflow cannot be met, then the parts must berebaked and resoaked according

20、 to 5.4 and 5.5. The time between reflows shall be 5 minutes minimum and 60 minutesmaximum.Note 1: All temperatures refer to the center of the package, measured on the package body surface that is facing up duringassembly reflow (e.g., live-bug orientation).If parts are reflowed in other than the no

21、rmal live bug assembly reflow orientation, (i.e., dead-bug orientation), Tpshall bewithin2Cofthelive bug Tpand still meet the Tcrequirements, otherwise the profile shall be adjusted to achieve thelatter.To accurately measure actual peak package body temperatures refer to JEP140 for recommended therm

22、ocouple use.Note 2: The oven should be loaded with the same configuration or verified equivalent thermal load when running parts orbeing profiled.Table 5-1 Moisture Sensitivity LevelsLEVELFLOOR LIFE4SOAK REQUIREMENTS3STANDARDACCELERATED EQUIVALENT1eV0.40-0.48eV0.30-0.39CONDITIONTIME CONDITION TIME (

23、hours) CONDITION TIME (hours) TIME (hours)1 Unlimited30 C/85%RH168+5/-085 C/85%RHNA NA NA2 1 year30 C/60%RH168+5/-085 C/60%RHNA NA NA2a 4 weeks30 C/60%RH6962+5/-030 C/60%RH120+1/-0168+1/-060 C/60%RH3 168 hours30 C/60%RH1922+5/-030 C/60%RH40+1/-052+1/-060 C/60%RH4 72 hours30 C/60%RH962+2/-030 C/60%RH

24、20+0.5/-024+0.5/-060 C/60%RH5 48 hours30 C/60%RH722+2/-030 C/60%RH15+0.5/-020+0.5/-060 C/60%RH5a 24 hours30 C/60%RH482+2/-030 C/60%RH10+0.5/-013+0.5/-060 C/60%RH6Time on Label(TOL)30 C/60%RHTOL30 C/60%RHNA NA NANote 1: CAUTION - To use the accelerated equivalent soak conditions, correlation of damag

25、e response (including electrical, after soak and reflow), should beestablished with the standard soak conditions. Alternatively, if the known activation energy (eV) for moisture diffusion of the package materialsisinthe range of 0.40 - 0.48 eV or 0.30 - 0.39 eV, the accelerated equivalent may be use

26、d. Accelerated soak times may vary due to material properties(e.g., mold compound, encapsulant, etc.). JEDEC document JESD22-A120 provides a method for determining the eV.Note 2: The standard soak time includes a default value of 24 hours for semiconductor manufacturers exposure time (MET) between b

27、ake and bag andincludes the maximum time allowed out of the bag at the distributors facility.If the actual MET is less than 24 hours, the soak time may be reduced. For soak conditions of 30 C/60% RH, the soak time is reduced by 1 hour foreach hour the MET is less than 24 hours. For soak conditions o

28、f 60 C/60% RH, the soak time is reduced by 1 hour for each 5 hours the MET is lessthan 24 hours.If the actual MET is greater than 24 hours the soak time must be increased. If soak conditions are 30 C/60% RH, the soak time is increased 1 hourfor each hour that the actual MET exceeds 24 hours. If soak

29、 conditions are 60 C/60% RH, the soak time is increased 1 hour for each 5 hours that theactual MET exceeds 24 hours.Note 3: Supplier may extend the soak times at their own risk.Note 4: Floor Life only relates to moisture/reflow related failures and does not take into consideration other failure mech

30、anisms or shelf life issues due tolong term storage.Note 5: Table 5-1 accelerated soak requirements may not apply to mold compounds that do not contain fillers.January 2015 IPC/JEDEC J-STD-020E7Table 5-2 Classification ProfilesProfile Feature Sn-Pb Eutectic Assembly Pb-Free AssemblyPreheat/SoakTempe

31、rature Min (Tsmin)Temperature Max (Tsmax)Time (ts) from (Tsminto Tsmax)100 C150 C60-120 seconds150 C200 C60-120 secondsRamp-up rate (TLto Tp) 3 C/second max. 3 C/second max.Liquidous temperature (TL)Time (tL) maintained above TL183 C60-150 seconds217 C60-150 secondsPeak package body temperature (Tp)

32、For users Tpmust not exceed theClassification temp in Table 4-1.For suppliers Tpmust equal or exceedthe Classification temp in Table 4-1.For users Tpmust not exceed theClassification temp in Table 4-2.For suppliers Tpmust equal or exceedthe Classification temp in Table 4-2.Time (tp)* within 5 C of t

33、he specified classi-fication temperature (Tc), see Figure 5-1.20* seconds 30* secondsRamp-down rate (Tpto TL) 6 C/second max. 6 C/second max.Time 25 C to peak temperature 6 minutes max. 8 minutes max.* Tolerance for peak profile temperature (Tp) is defined as a supplier minimum and a user maximum.No

34、te 1: All temperatures refer to the center of the package, measured on the package body surface that is facing up during assembly reflow (e.g., live-bug). Ifparts are reflowed in other than the normal live bug assembly reflow orientation (i.e., dead-bug), Tpshall bewithin2CofthelivebugTpand stillmee

35、t the Tcrequirements, otherwise, the profile shall be adjusted to achieve the latter. To accurately measure actual peak package bodytemperatures, refer to JEP140 for recommended thermocouple use.Note 2: Reflow profiles in this document are for classification/preconditioning and are not meant to spec

36、ify board assembly profiles. Actual board assemblyprofiles should be developed based on specific process needs and board designs and should not exceed the parameters in this table.For example, if Tcis 260 C and time Tpis 30 seconds, this means the following for the supplier and the user:b For a supp

37、lier: The peak temperature must be at least 260 C. The time above 255 C must be at least 30 seconds.b For a user: The peak temperature must not exceed 260 C. The time above 255 C must not exceed 30 seconds.Note 3: All components in the test load shall meet the classification profile requirements.Not

38、e 4: SMD packages classified to a given moisture sensitivity level by using Procedures or Criteria defined within any previous version of J-STD-020,JESD22-A112 (rescinded), IPC-SM-786 (rescinded) do not need to be reclassified to the current revision unless a change in classification level or ahighe

39、r peak classification temperature is desired.IPC-020e-5-1Figure 5-1 Classification Profile (Not to scale)Tc-5CtMax. Ramp Up Rate = 3C/sMax. Ramp Down Rate = 6C/s Preheat AreaTsmaxTsmintsTpTLTemperatureTime25Time 25C to PeakSupplier Tp Tc- Supplier tpTcUser Tp10% along any polymeric film bridging any

40、 metallic features that is designed to be isolated(verifiable by through transmission acoustic microscopy).d. No delamination/cracking 50% of the die attach area:1. In packages with exposed die pad used for thermal conductivity or2. For devices that require electrical contact to the backside of the

41、diee. No surface-breaking feature delaminated over its entire length. A surface-breaking feature includes lead fingers, tie bars,heat spreader alignment features, heat slugs, etc.6.2.1.2 Substrate Based Packages (e.g., BGA, LGA, etc.):a. No delamination on the active side of the die.b. No delaminati

42、on on any wire bonding surface of the laminate.c. No delamination change 10% along the polymer potting or molding compound/laminate interface for cavity and over-molded packages.d. No delamination change 10% along the solder mask/laminate resin interface.e. No delamination change 10% within the lami

43、nate.f. No delamination/cracking change 10% through the die attach region.g. No delamination/cracking between underfill resin and chip or underfill resin and substrate/solder mask.h. No surface-breaking feature delaminated over its entire length. A surface-breaking feature includes lead fingers, lam

44、inate,laminate metallization, PTH, heat slugs, etc.Note 1: On substrate based packages, the C-mode acoustic image is not easy to interpret. Through Transmission AcousticImaging is recommended to supplement and verify the C-mode images because it is easier to interpret and more reliable. Ifit is nece

45、ssary to verify results or determine at what level in the package the cracking/delamination is occurring, cross-sectional analysis should be used.6.2.3 Moisture Induced Body Warpage during Board Assembly of Substrate Based Packages (e.g. BGA, LGA, etc.)Moisture Induced warpage could result in solder

46、 bridging or open connections during board assembly solder attachmentoperations. It is known that ingressed moisture can either increase or decrease the total package body warpage dependingon the specific design of the component. Total package body warpage can be a function of the moisture content a

47、nd can beaffected by the ramp rates and dwells used to measure the total warpage effect at elevated temperatures. Package body war-page measured per JESD22-B112 should be characterized during package development and any time there are changes ofthe type denoted in section 4.3. Ability to attach comp

48、onents that exhibit warpage can be verified by using board assembly.6.2.4 Bare Die with Polymer Layers Currently J-STD-020 does not provide failure criteria for the package style of baredie with polymer layers. Any party choosing to use the procedures within this standard to determine MSL rating for

49、 thistype of package style is responsible for defining the appropriate failure criteria to ensure the long term reliability of thedevice.6.2.5 Non-IC Packages Currently J-STD-020 does not provide failure criteria for non-IC package styles. Any partychoosing to use the procedure within this standard to determine the MSL rating for a non-IC package is responsible fordefining the appropriate failure criteria to ensure the long term reliability of the device.6.3 Failure Verification All failures should be analyzed to