JEDEC J-STD-609A 01-2011 Marking and Labeling of Components PCBs and PCBAs to Identify Lead (Pb) Lead-Free (Pb-Free) and Other Attributes.pdf

1、JOINTINDUSTRYSTANDARDMarking and Labelingof Components,PCBs and PCBAs toIdentify Lead (Pb),Lead-Free (Pb-Free)and Other AttributesIPC/JEDEC J-STD-609A-201)HEUXDUSupersedes:IPC/JEDEC J-STD-609A - March 2010IPC and JEDEC Standards and Publications are designed to serve the public interest throughelimi

2、nating misunderstandings between manufacturers and purchasers, facilitating interchange-ability and improvement of products, and assisting the purchaser in selecting and obtainingwith minimum delay the proper product for his particular need. Existence of such Standardsand Publications shall not in a

3、ny respect preclude any member or nonmember of IPC orJEDEC from manufacturing or selling products not conforming to such Standards andPublications, nor shall the existence of such Standards and Publications preclude theirvoluntary use by those other than IPC or JEDEC members, whether the standard is

4、 tobe used either domestically or internationally.Recommended Standards and Publications are adopted by IPC or JEDEC without regardto whether their adoption may involve patents on articles, materials, or processes. By suchaction, IPC or JEDEC do not assume any liability to any patent owner, nor do t

5、hey assumeany obligation whatever to parties adopting the Recommended Standard or Publication.Users are also wholly responsible for protecting themselves against all claims of liabilitiesfor patent infringement. The material in this joint standard was developed by the Marking,Symbols and Labels for

6、Identification of Assemblies, Components and Devices Task Group(4-34b) of the Materials Identification Subcommittee (4-34) and JEDEC Committee JC14.4Quality Processes and Methods.For Technical Information Contact:JEDECSolid State Technology Association3103 North 10th Street, Suite 240-SArlington, VA

7、 22201-2107Tel 703 907.Fax 703 907.7501IPC3000 Lakeside Drive, Suite 309SBannockburn, Illinois60015-1249Tel 847 615.7100Fax 847 615.7105Please use the Standard Improvement Form shown at the end of this document.Copyright 2011 JEDEC Solid State Technology Association, Arlington, Virginia, and the IPC

8、, Bannockburn, Illinois, USA. All rights reservedunder both international and Pan-American copyright conventions. Any copying, scanning or other reproduction of these materials without theprior written consent of the copyright holder is strictly prohibited and constitutes infringement under the Copy

9、right Law of the United States.IPC/JEDEC J-STD-609A.01-2011Marking and Labelingof Components, PCBsand PCBAs to IdentifyLead (Pb), Lead-Free(Pb-Free) and OtherAttributesA joint standard developed by the Marking, Symbols and Labelsfor Identification of Assemblies, Components and Devices TaskGroup (4-3

10、4b) of the Materials Identification Subcommittee (4-34)and JEDEC Committee JC14.4 Quality Processes and MethodsUsers of this publication are encouraged to participate in thedevelopment of future revisions.Contact:JEDECSolid State Technology Association3103 North 10th Street, Suite 240-SArlington, VA

11、 22201-2107Tel 703 907.0026Fax 703 907.7501IPC3000 Lakeside Drive, Suite 309SBannockburn, Illinois60015-1249Tel 847 615.7100Fax 847 615.7105Supersedes:IPC/JEDEC J-STD-609A -March 2010JESD97 - May 2004IPC-1066 - January 2005IPC/JEDEC Joint Standard J-STD-609A.01 1 Foreword Directive 2002/95/EC of the

12、 European Parliament and of the Council on the restriction of the use of certain hazardous substances in electrical and electronic equipment, commonly referred to as the “RoHS Directive1”, and other legislation are driving the electronics industry towards the use of lead-free (Pb-free) solders and c

13、omponents with Pb-free 2ndlevel interconnect terminal finishes and materials. There are different Pb-free solders being used for the various soldering operations in electronics. Each of these solders may require different processing temperatures for assembly, rework, and repair. Some means of commun

14、icating the identity of the Pb-free or Pb-containing solder must be provided so that those performing assembly, rework and repair are aware of the temperature capabilities and limitations of these solders, and are able to distinguish between Pb-free and Pb-containing solders. Marking of components a

15、nd/or labeling their shipping containers are needed to identify and distinguish Pb-containing and Pb-free 2ndlevel interconnect terminal finishes and materials. Labeling electronic assemblies using Pb-free solder materials will facilitate end-of-life recycling of electronic equipment. This standard

16、sets forth minimum requirements and includes options for the provision of additional information. This paradigm shift to Pb-free electronics has created a need for identification of traditional Pb-containing coatings, finishes and solders. This standard can be utilized to identify the presence of Pb

17、 for those markets as described in Sections 5 (Marking/Labeling Categories) and 8 (Marking and/or Labeling of Pb-Containing Components, PCBs, and PCB Assemblies). This standard supersedes JESD97 and IPC-1066. 1The RoHS Directive itself is not a law; rather, it is a direction to the European Union Me

18、mber States to implement their own laws embodying the requirements of the Directive. These laws were required to be in effect as of July 1, 2006. IPC/JEDEC Joint Standard J-STD-609A.01 Page 1 Marking and Labeling of Components, PCBs and PCBAs to Identify Lead (Pb), Lead-Free (Pb-Free) and Other Attr

19、ibutes (From JEDEC Board Ballot JCB-10-18, formulated under the cognizance of the JC-14 Committee on Quality and Reliability of Solid State Products and the IPC 4-34 Subcommittee on Materials Identification.) 1 Scope This standard applies to components and assemblies that contain Pb-free and Pb-cont

20、aining solders and finishes. This standard describes the marking of components and the labeling of their shipping containers to identify their 2ndlevel terminal finish or material, and applies to components that are intended to be attached to boards or assemblies with solder or mechanical clamping o

21、r are press fit. This standard also applies to 2ndlevel terminal materials for bumped die that are used for direct board attach. This standard applies to boards/assemblies, to identify the type of Pb-free or Pb-containing solder used. This standard documents a method for identifying board surface fi

22、nishes and Printed Circuit Board (PCB) resin systems. This standard applies to PCB base materials and for marking the type of conformal coating utilized on Printed Circuit Board Assemblies (PCBAs). Material and their containers previously marked or labeled according to JESD 97, IPC-1066, or previous

23、 versions of this standard need not be remarked unless agreed upon by the supplier and customer. Labeling of exterior surfaces of finished articles, such as computers, printers, servers, and the like, is outside the scope of this standard. However internal PCBs and PCBAs are covered by this standard

24、. Labeling of retail packages containing electronic products is also outside the scope of this standard. 1.1 Purpose This standard provides a marking and labeling system that aids in assembly, rework, repair and recycling and provides for the identification of: 1) those assemblies that are assembled

25、 with Pb-containing or Pb-free solder; 2) components that have Pb-containing or Pb-free 2ndlevel interconnect terminal finishes and materials; 3) the maximum component temperature not to be exceeded during assembly or rework processing; 4) the base materials used in the PCB construction, including t

26、hose PCBs that use halogen-free resin; 5) the surface finish of PCBs; and 6) the conformal coating on PCBAs. IPC/JEDEC Joint Standard J-STD-609A.01 Page 2 2 Reference Documents 2.1 IPC URL: www.ipc.org IPC-T-50, Terms and Definitions for Interconnecting and Packaging Electronic Circuits IPC-CC-830,

27、Qualification and Performance of Electrical Insulating Compound for Printed Wiring Assemblies (Conformal Coating) IPC-4101, Specification for Base Materials for Rigid and Multilayer Printed Boards 2.2 JEDEC URL: www.jedec.org JESD88, JEDEC Dictionary of Terms for Solid State Technology 2.3 IEC URL:

28、www.iec.ch IEC 61249-2-21, Materials for printed boards and other interconnecting structures - Part 2-21: Reinforced base materials, clad and unclad - Non-halogenated epoxide woven E-glass reinforced laminated sheets of defined flammability (vertical burning test), copper-clad 2.4 European Parliamen

29、t URL: http:/ec.europa.eu/environment/waste/weee/index_en.htm Directive 2002/95/EC of the European Parliament and of the Council on the Restriction of the Use of Certain Hazardous Substances in Electrical and Electronic Equipment. 2.5 ANSI URL: www.ansi.org/ ANSI 17-1981 Character Set for Optical Ch

30、aracter Recognition (OCR-A) IPC/JEDEC Joint Standard J-STD-609A.01 Page 3 3 Terms and Definitions Other than those terms listed below, the definitions of terms used in this standard are in accordance with IPC-T-50 and/or JESD88. 3.1 2-D code label (matrix) A label that contains data in two dimension

31、s as either stack or matrix types. 3.2 2Li (or 2LI) Abbreviation for 2ndlevel interconnect. 3.3 base materials The laminates and/or the prepregs used to fabricate the printed circuit board. NOTE A prepreg is a sheet of material that has been impregnated with a resin cured to an intermediate stage, i

32、.e., B-staged resin. (Ref: IPC-T-50) 3.4 component An individual part such as a connector, capacitor, integrated circuit, socket, multichip module, or hybrid circuit, etc. 3.5 halogen-free board Printed board resins plus reinforcement matrix that contain maximum total halogens of 1500 ppm with less

33、than 900 ppm bromine and less than 900 ppm chlorine (per IEC 61249-2-21). 3.6 homogeneous material A material of uniform composition throughout that cannot be mechanically disjointed into different materials. Mechanically disjointed means that the materials can, in principle, be separated by mechani

34、cal actions such as: unscrewing, cutting, crushing, grinding, and abrasive processes. 3.7 intct (or INTCT) Alternative abbreviations for the word “interconnect.” 3.8 linear bar code label A label that gives information in a code consisting of parallel bars and spaces. 3.9 material category Solder pa

35、ste, lead/terminal finish, or terminal material/alloy of the solder balls used to make the 2ndlevel interconnect. 3.10 maximum component temperature The temperature that a component should not exceed during assembly as measured on the top of the component body. IPC/JEDEC Joint Standard J-STD-609A.01

36、 Page 4 3 Terms and Definitions (contd) 3.11 Pb-free; lead free Having a concentration of Pb with a maximum concentration value of 0.1% by weight in each homogenous material. NOTE Component and end-product suppliers may desire to clarify this important distinction (between 0% and 0.1% Pb) with their

37、 customers. 3.12 Pb-free symbol A symbol that can be used in place of the phrases “Pb-free” or “lead-free”. See Figure 4-2. 3.13 second (2nd) level interconnect The connection made by attaching a component to a printed circuit board. See Figure 3-1. This connection is external to the component, not

38、internal. Figure 3-1 Examples of materials that comprise the 2ndLevel Interconnect 3.14 second (2nd) level interconnect component label A label placed on boxes and bags that contain components with either Pb-containing or Pb-free terminal materials/finishes. This label includes the material category

39、 and maximum component temperature (see 3.12 and 3.13). See Figure 4-3 for label formats for components with Pb-containing finishes/materials and Figure 4-4 and Figure 4-5 for components with Pb-free finishes/materials. 3.15 second (2nd) level interconnect terminal finish or material The material at

40、 the component 2ndlevel termination referred to in Figure 3-1. Depending on the component type this material could refer to the terminal finish or ball material. IPC/JEDEC Joint Standard J-STD-609A.01 Page 5 4 Symbols, Labels, and Marks 4.1 Material Category Symbol This symbol (see Figure 4-1) is us

41、ed to identify a terminal finish or material listed in 5.3. Figure 4-1 Example of mark indicating material category 2 and the optional circle, ellipse, underline or parentheses NOTE 1 If the Materials Category is used without a circle, ellipse, parentheses or underline, it must be made clear that th

42、e marking defines the category e.g. “Category = e2”, or “Solder = e2” NOTE 2 The letter “e” would be replaced with a “b” for identifying surface finish material listed in 5.2 for PCBs. 4.1.1 Size and Location The size and location are discretionary, but shall be legible to corrected, unmagnified vis

43、ion. 4.1.2 Color The color for the e and category number should be selected to provide sufficient contrast to be legible to corrected, unmagnified vision. The color red should be avoided as red suggests a personal hazard. 4.1.3 Font The font style should be “Arial”, “OCR-A” or equivalent. 4.2 Pb-fre

44、e Symbol This symbol (see Figure 4-2) can be used in addition to, or instead of, the phrase “Pb-free.” Figure 4-2 Pb-free Symbol IPC/JEDEC Joint Standard J-STD-609A.01 Page 6 4 Symbols, Labels, and Marks (contd) 4.3 Second (2nd) Level Interconnect Component Label This label (see Figure 4-3, Figure 4

45、-4, and Figure 4-5) is used to indicate the 2ndlevel interconnect terminal finish or material category (Clause 5) and maximum component temperature. The Pb-free symbol (See 4.2) may be appended after the terms “2ndLevel Interconnect” as indicated in Figure 4-5. This use of the Pb-free symbol applies

46、 only to the 2ndlevel interconnect and should not be interpreted as an indication that any other part of the component is Pb-free. This label, if used, is placed/printed on the lowest level shipping container and any “ESD”, ”Dry pack” or other bag/box, excluding tubes, trays, reels or other carriers

47、, within the lowest level shipping container. Figure 4-3 Example of 2ndLevel Interconnect Component Label indicating a Pb-containing material Figure 4-4 Example of 2nd Level Interconnect Component Label indicating a Pb-free e2 material with a maximum component temperature of 260C Figure 4-5 Example

48、of 2nd Level Interconnect Component Label utilizing the Pb-free symbol indicating both Pb-free material with category and maximum component temperature indicated on adjacent label IPC/JEDEC Joint Standard J-STD-609A.01 Page 7 4 Symbols, Labels, and Marks (contd) 4.3.1 Size It is recommended that the

49、 label be a minimum of 75 mm by 50 mm. 4.3.2 Color The label shall be black letters/symbols on a white or contrasting background. 5 Marking/Labeling Categories These categories are for the technical purposes of this standard and are not to be used for determining regulatory compliance. 5.1 PCB Base Material Categories The PCB base materials may be identified by using the classification system found in IPC-4101, where a unique Specification Sheet (“slash-sheet”) number identifies a specific grade of material. Some of the common bas