JEDEC JEB15-1969 Terminology and Methods of Measurement for Bistable Semiconductor Microcircuits《双稳半导体微电路测量的术语和方法》.pdf

1、EIA JEBLS 69 m 3234600 0002955 5 m c i DECEMBER 1969 JEDEC ENGINEERING BULLETIN No. 15 I Terminology and Methods of Measurement for Bistable Semiconductor Mic rocircu its ELECTRONIC INDUSTRIES ASSOCIATION 2001 Eye Street, N.W.* Wdhgton, D.C. 2ooo6 Published by ELECTRONIC INDUSTRIES ASSOCIATION EnCli

2、neering Department 2001 EE STREET. N.W WASHINGTON, D. C. 206 I EIA JEBLS b9 W 3234b00 0002957 9 W s 4 TZRMINOLOGY AND MiTHODS OF MEASURE“l FOR BISTABLE SWCONDUCTOR MICROCIRCUITS I! Guide to the Use of EIA Format MED-32-3A, “Registration Data for Semiconductor Integrated Bistable Logic Circuits“ This

3、 bulletin explains the terminology an2 methods of measurement for bistable semiconductor microcircuits, It is also intended to be used with the EIA Reg- istration Data Format for Semiconductor Integrated. Bistable Logic Circuits. The ptirpose of this bulletin is to provide guidance at each section o

4、f the for- mat. ular section referenced and direction in using the particular section, This guidanca 2s given as an explanation as to the intent of the partic- 6 1.0 Gefieral This format is intended for the registration of semiconductor inte- grated bistable logic circ-dta including .monolithic, mul

5、tichip, fihl 0 and hybrid bistable circuits, A semiconductor integrated logic circuit is a single package circuit in vrhich: a. No external elements are required to perform the registered f mction; b, The contained elements are inseparably associated; C, The contained elements are tested and used as

6、 logic circuits. EIA JEBL5 69 m 3234600 O002958 O m I. O General (continued) A bistable logic circuit is defined as one having an output which can be at either of two levelg (an output which is stable in two states). Its output is indefinitely stable after removal of the input signal whioh caused it

7、 to go to that level, circuit whose output has two .possible levels but which requires the re- This differentiates it from a logic gating tention of the input signals to retain the output level, mis also dif - ferentiates the bistable circuit fmm the monostable and astable circilits. The state of a

8、bistable refers to a particular and specified pin (Para. 2.1 of format). This pin cdn, under normal operation, be at one of twu levels. The voltage (or current) at that pin is normally and discretely at a high or low level. In positive logic the “HIGH (H)“ voltage (or current) level is the more posi

9、tive than the tlLOW (IL)“ voltage (or current)level. If the pin specified in Para. 2.1 is at the “H1Gi-P level, then the bistable is in the lliiGItt state. In the format when reference is made to the state of the bistable the pin specified in Para. 2.1 of the format is considered having an output wh

10、ich must be gated so that the state of the bistable In bistables O can be determined, where reference is made .t;O the state of the bistable, it is assumed that the circuit is gated so thzt the state of the bistable will be reflected at the output. This format is written to include ail logical forms

11、 of bistable circuits. It is also intended to be used for registration of all circuit configura- tions used to achieve the variety of logical forms of bistkbb circuits. / EIA JEBLS b9 m 3234b00 0002959 2 m 1.0 Qcnor;il (continuod) Thoroforo, oomo p;ircunotora aro not qplicnblo to SOMO forms of bist;

12、iblo O circuito. cnblo to b3tables having only asynchronouo inputs,) paramoixr i3 not appLicable to a paZrt;icubr circuit bo- rogiaterod At should bo so statod on tho registration and eound tocMc clock and oynchromo pnrcmotors *aro not appli- ln ca3ea orrtlod to oonlrol the aoiPrrip.f;anao OP rejeot

13、im of o3.gndl.s appUed to the synchronous termina(a) anci/. then they eh0d.d be noted here and their function described, .I Outputb) Every teqnba2 from tho bistable logic circuit which is used to rivo or provide signals to other logicelemonts or devicoa shall be clarrsi- fiod as an output. The btent

14、 of WS soctd.on is to define how thcm outwts may be used logically Tho registration shU call. ou$ those outputs which can be connected with similar outputs to do logicr If the state of the bistable logic circuit can be changed by applying signals to the outputs this should also be called out, I EIA

15、JEBLS b m 3234600 0002bL O m 5 leb Output (5) (continued) This indicates the degree of isolation between the output and the bistable pmtion of the bistable logic circuit. 2.0 LOGIC - GZNEiUL The 1i)gi.c Df switching circuits deals with variables which can take on only one of two states. signal line

16、shall be referred to as. the A ci.rci2i.t can be characterized either uith positive logic or negative logic; actually both can be applied to any device. intended to be used predominantly with one or the other logic conventions The states which can exist on a teminal or a state and the HIGH state. Bu

17、t, ii“ a circuit is then it should be registered in that fashim. logic could (not must) be restated for the opposite logic convention. If ail signal Une teminals in a logic diagram of a device have the sane pair of physical states and if the more positive potential (current) is consistently seleoted

18、 as the HIGH level, the logic description of the .device is said to have positive logic, It should be noted Chat the If the less positive potentid, (current) 3s consistently selectad as the WIGii XVXL, the device is said to have negative logic, is assurned for this format. it must be so stated. Posi

19、tive logic If negative logia is reqpred by application, 2.1 Logic. Xagram - Qoneral Logic diagrais are graphicai symbols which descfibe devices or systems which contain only two-state variables. mie purpose of providing-:a logic diagram 5s this fonnat is to assist the user in imderstmdlng the opepat

20、ion of the device without need2ng to refer to or completely understand the electriccil equivalent circuitry Involved in inplementing the device. is the subjeck of registration by this forkt ra%her than Note that the bistable device a black box EIA JEBLS 69 m 3234b00 0002762 2 m r 3 6 2.1 hcio DFqrm

21、- Gonord. (continuo) tho circuitry uood to implomont Lho doVLco. A logia infirm ahoud provio tho u30r tbth LQ much infomt.Lm regwdjng clovico wo a3 ia po 3 sible, XloLcal Sub-hnctiono in many biotablo dovico somo 1 giod. 8uu-fwotion is porfonn d cm the synchronous (or other) inputs. sub-wctiona as o

22、utlinad 5.n Stmdd graphical symbols for them USAS1 Y32.l.b should be usod (tho r0c”Cungular bioO make the loians Ail pertinent 10gj.c: temin6i.s should be identified with respect to pin number, It is of operation is that tho aaynchronous inputs caum as well as dotonnino tho stoto of a doVi,coo wlior

23、oae tho synohronoiio input3 dstsnalno tho stab of the output only aftw a clock sigiii, has becn applisd. Hcnco the timo dolay betwoen aspchronoun input variations and output variations is determinod by Mie qeod of the circuit and 13, for ors, the LUd levels am released and the HIGH levels (cross-cou

24、pled fmm the wbput) EIA JEBLS 67 = 3234b00 O002767 L un I. 0 2.21 JD gates cannot vn !I Q Q nn LLHH HLLH - exist in the LOI1 level sirnultmeously; a race occurs and it cannot 5e predicted which outpt will reach the LOU level first anci. the state 6f the outgmt is inde.t;emdnate. the effect is given

25、below: The truth table which describes ci ange) In most cases it is assumed that the last level. on the synchronous inputs just before the activating edge of the clock is the one that-will be rec- ognized. ing at the clock edge may be recognized. In the circuit shown on Page 10, if the clock goes hi

26、gh and the S or R terminal momentarily oges to “L“ the capacitor ill charge and may not discharge before the clock edge even though the input goes back to“B“ and the clock will recognize the “L“. The truth table should note this by a footnote which sayc“wil1 store a momentary “L“ (or H1) level, I Ho

27、wever, in some bistable designs some level prior to that exist- Rsynchronous Mode For tne asynchmrnous Node of operatj.on, the truth table describing the operatim is given Scltw: ( hence, in the algebra the afore- mentioned sjtmbds +, ard may be treated as different functions wen though the function

28、 refers to the same terminal or signai Ene. 2.3.1 The Logic Equatton and tne Truth Table The logic equation supports the trutn table in asserthg the con- ditions required to obtain a HIGH (H) at the output either at timo (n-tl) in the case of synchronous operation, or at time n in the case of asynch

29、ronous operation, describe the “dmlt care“ condi.ti.ons such as illogical entries or entries which lead to indeteminate putputs. sxpport 5he trtith table, therefore, equations which define input I Separate logic eqyations should in order ta filly restrictions should aLso be provided. Consider the sy

30、nchronous mode of operation- of the bistable device discussed in Section 2,2,1/2,2.2, The truth table is: Tim loF$.c equation which speolfiee when Qn+l a 1 is - R+l a s %a + sn vauo of voltago, curront m/or tmpraturo which ia to bo axcoodod ony at tho riok of pormanontlydltrlry: tho chwac- toriritic

31、ri of tho bictablo. A combination of TocudJMLm limitsi caruzol normally 4.1.1 Storqe Temporaturo Range defines the range of enwonment in which a bistable my be storad with no eloatrical aonnoatone to the device . 4.1.2 Tam;iorature Range undor Bias definos the temperature range which tho bistable ma

32、ybe operated whcn it is in a noind operating mode. One should be oognizant of the fact that %f operating temperature rqo is cpcified, electrical characteristics mutt be registered at tho temperature =tremes. 4.2 Tem flaws into a Low Thio is true regard2eeo of whether it 18 an or an outiput. I- EIA J

33、EBLS b9 3234b00 0002976 2 M 20 The following diagram shows positive current I- _- - ./- - - + II d +Io r. The fnllowjng diagram shows negative current Magnitude - For niii*poses of registration the magnitude only is considered when comparing a current, Therefore, a maximum current w!iich is negative

34、 is its greatest magnituder t.han -lmA), (-1m;A is larger i4here a parameter limit is a maximum negative current, B. VoItge Direction and Sign A voltage is always measured in relation to a reference pointe Thia i3 generally ground or a common pin. The positive terminal is that one into which electro

35、ns flow when the two terminals me T Li EIA JEBLS 69 3234600 0002977 4 22 B. Voltago (continuod) cumctad togothor. in rolation to tho qxcified tominal or reference. A voltqo rxan thon bo positive or nogative hist as in ourront, .sign is not oonoidarad when ranking sarating Condltions T;G saotion desc

36、ribes the powor supply voltqps and teqerqturo for which ogeration is cl;Limod, In additrton it deaoribes the test techniquo used to verify proper operation. 5.21 Noininal. Supply Voltages Wile a circuit may operate over a range of powor supply voltages, it.is generally true that optimum operation oc

37、ours at a specific voltage. and denote the pin to which it is applied. the voltages be referonced to a common ground pin; if this is not true, it should be darified hher defini%ions suoh as percent or magnitude varLation perinissiblo, Show here the nominal. supply voltass to be cqplied It is intende

38、d that The registrant may add S.l.2 por ating Temperature n* will define the restrictiono an .the devices uapnbzUty to oprato trithin the tanperaturo spootrum. 5.1.2.1 l7a8 dosoribes the dofktion of the 25OC conitiion ao t;O whQthQr it is ambient or oaso. Either oonbitim may be usod to dafino-the el

39、eOtriO8l aharaotoriatics. 4 I EIA JEBL5 b9 m 3234600 0002978 b m 22 r,m then statio I charactori D.C, Stabilized tasts are made after d.2. transients induced by oporatine oonditions have ondcd. Eleatricd. and Themcd. stabidty have beon reachad, Adcedithe elec.t;rical conditions for txsting tho param

40、- stor have been applied long enough Ki stability bu$ ,the themal. condition may not have reach elootrhd. stabilj_aed. true, that is, the thermal oonditins are considered to be the same as they were before any eleoLdcaJ, conditd.ons were introduced. applied for automatio, high speed testing. In faot

41、, tho converae is often considered Tlds concept 18 generqw It is obvious that for repeatabiity and interchangeability the timo and dutg cyole of tho applied voltageo aro very importqpt and must be defined hero. Even though tb.measuremon$ tochnique is definou as.pdaed the parameters mawed are stU oon

42、sidered to be the statio oharaoterlstioer Tds motion : defines parameters which are measured at the time the r C EIA JEBLS 69 E 3234600 0002979 E 23 5. 2 Static Characteristics (continued) bistable device is in a stable electrical. logical state. This O stable state tll be the result of a static inp

43、ut and output applied electricai conditions. To achieve khe required state may have taken a sequence of electrical cmditions (pulses) or it may have been achieved by statically forcing the condition through input or output terniinais. Regardless of the technique used, t-he is not considered a variab

44、le; the parameter measurement is uneffected by time (except as described in 5.1.2.3) . The introductqr paragraph in Uie fornnt for this section provides expansion of its htent. 5.2.1 JlnCt the refemnoe voltage at eaah parameter EIA JEBLS b9 = 3234b00 O002983 b 5.2.3 Reference Voltage (continued) e I

45、f the latter choice is made then the tolerance for these reference This characteristic is .intended t;o define the maximum (5.2,4,1) and minimum (5.2.k.Z) W Level of the bistable oiit,put(s) under Worst caso conditions of input levels and output loading. a 5.2*4*1# .va OL xu . is defined for two con

46、ditions. First, in !L2.k.1.i8 v.0 stable conditions, maximum is determihed under nod internal All inputs (asynchronous and synchronous) are at worst case levels for this stable state, but are not intended to force the state, held by asynchronous inputs which are then at their worst case in !kL!.A2,

47、the output state is forced and levels. Par% s,Z,k.l.l applies to any type of bistable circuit and must be specified whoreas 5020401.2 may or may not be applicable depending on the particular type of circdL Figure 5.2.4,I shows two examples of applying 5.2,bl.l and 5.2.k.l.2 to basic WL and LI7.L bis

48、table circuits. The V 09i, logic gates) this characteristics is primarily intended for ECL type circuits although it is eqyal3.y applicable to other types. minimum is defined in 5.2,k,2 aaid (as is the case for However, in cases such as MIL it is recommended to specify Ulis characteristic as zero vo

49、lts rather Uian determine the actual minhum. which will make the output level in quastim a minimum, either holding or not - holding the bistable in this state, whichever is worse, For a specific ECL circuit example, see Figure S,2.4.2, in any case, all inputs must be at that mrst case leve,2,5.l where the Ia Bm is used. For other types of circuits this is referred to as short I . circuit current. “his characteristic defines all (asynchronous and synchronous and clock) input currents for both HIW and Wd levels. A ma