JEDEC JEP118-1993 Guidelines for GaAs MMIC and FET Life Testing《GaAs MMIC和FET寿命试验导则》.pdf

1、i F e 5 z W II EIA JEPLLB 73 W 3234600 0504097 114 W Regmduccd By GLOBAL ENGINEERING DOCUMENTS With lha Permission d EIA Under Royalty Aveement JEDEC PU B LI CATION Guidelines for GaAs MMIC and FET Life Testing JEPll8 JANUARY 1993 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT EIA JEPLLB 9

2、3 = 323qbOO 0504098 050 NOTICE JEDEC Standards and Publications contain material that has been prepared, progressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. JEDEC Standards and Publications are designed to seNe the p

3、ublic interest through eliminating misunderstandings between manufacturers and purchases, facilitating interchangeability and improvement of products, and assisting the purchaser is selecting and obtaining with minimum delay the proper product for his particular need. Existence of such standards sha

4、ll not in any respect preclude any member or nonmember of JEDEC from manufacturing or selling products not conforming to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members, whether the standard is to be used either domestically or i

5、nternationally. JEDEC Standards and Publications are adopted without regard to whether their adoption may involve patents or articles, materials, or processes. By such action, JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the

6、JEDEC Standards or Publications. The information included in JEDEC Standards and Publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC Stand

7、ard or Publication may be further processed and ultimately became an EIA Standard. Inquiries, comments, and suggestions relative to the content of this JEDEC Standard should be addressed to the JEDEC Executive Secretary at EIA Headquarters, 2001 Pennsylvania Ave., N.W., Washington, D.C. 2ooo6. Publi

8、shed by ELECTRONIC INDUSTRIES ASSOCIATION Engineering Department 2001 Pennsylvania Ave., N.W. Washington, D.C. 2ooo6 PRICE: Please refer to the current Catalog of EIA e 1 1 2 2 2 3 3 4 4 4 5 6 6 7 7 7 8 8 8 9 11 I EIA JEPLLB 93 W 3234600 0504LOL 475 W JEDEC Publication No. 118 . Page 1 GUIDELINES FO

9、R Ga usually the median lifetime (50% failure) is used for this purpose. The standard method for predicting device lifetime where this value is too large to be measured directly is to run a series of life tests. Generally, only one parameter, usually the device temperature, is varied. A lifetime is

10、obtained at each temperature. These values are then extrapolated to the temperature of interest. In other cases, the objective may be simply to determine the lifetime at a given temperature. The purpose of this document is to define a standard approach for evaluating the expected life of GaAs MMICs

11、so that results from different life tests can be compared and so that a user of MMICs can predict a lifetime for his application. It is assumed in the wording of this document that the Mh4IC contains at least one FET, but the use of this document has no such limitation. Furthermore, the wording sugg

12、ests that the failures occur at the FEZ if this is not the case, then the stresses, tests and failure criteria need to be re-evaluated to ensure that they are appropriate to the failing component. To perform the life tests, a sample of devices is selected from the lot and is subjected to a stress in

13、 excess of normal use conditions to decrease the lifetime. The devices used can be MMICs. Alternatively, the lifetime of MMICs can be determined by determining the failure rate vs time of component structures within the MMIC, e.g., FETs, resistors, capacitors and bond wires, given the structure and

14、temperature profile of a MMIC. This latter calculation is not a straightforward one and a specific procedure is not addressed in this document. If it is assumed that the failure mechanisms are independent, the percentage of MMICs surviving to a given time is the product of the percentages of surviva

15、l of each component. Conducting accelerated tests of these devices can be very difficult because of the complexity of determining the channel temperature, the high cost of large sample sizes (especialiy where radio frequency (RF) stressing is performed) and the need to extrapolate to the temperature

16、s of actual device use. In particular, any difference in the techniques for determining the device thermal resistance that changes the thermal resistance value wiU have substantial impact on the corresponding predicted failure rate. However, the task of standardizing a method for determining channel

17、 temperature is stili in progress. JEDEC STANDARD JESD22-Ala-A provides a general description of life testing and serves as a guide, primarily regarding equipment. The provisions of that document are not considered binding here. 2. SCOPE Life tests are run for various purposes. Tests run to detect t

18、he level of infant mortality involve short time durations; unless the percentage of devi otherwise, Ids, drain-gate voltage at a leakage current of 1 mA/mm channel width, and, for the bias used in the stress, operating current, transconductance, and S-parameters should be included. Power and general

19、-purpose devices shall have 1 dB compression point and, if possible, gate current, measured, while low noise devices shall have noise figure data. RF data shall be taken as a function of frequency and include a point in the center plus one point at each end of the band of interest for the device. Th

20、ese measurements will serve as the reference points to compare against subsequent data to determine the level of degradation that has taken place; consequently no change in the test conditions or tuning shall be made. Measurement may be performed at any baseplate temperature at or below 125C. Therma

21、l resistance shali be determined using infrared scan or any other test or modeling technique that becomes widely accepted after these guidelines are issued. Experimental data shall be taken on at least 10% of the devices used for the life test to verify consistency. If the standard deviation of thes

22、e measurements multiplied by the device power dissipation is no greater than SOC, the average value may be EIA JEP11B 93 = 3234600 0504103 248 JEDEC Publication No. 118 Page 3 used for all devices; if not, then the relative thermal resistance of each device must be measured and used to determine the

23、 actual difference between case and channel temperature. If a series of life tests is being run at different temperatures, the device thermal resistance shall be determined at the case temperature of the second highest (+/- 25C) steady state life test temperature. If infrared scan is used, appropria

24、te correction shall be made for infrared emissivity. For packaged devices, if infrared scan or liquid crystal is used, an electrical method shall be used to adjust the thermal resistance for the effect of the package lid; to do this, measure the device temperature using the electrical method (or oth

25、er accepted method) before and after the lid is applied, calculate the increase in temperature, and add this to the value determined on the unlidded device. The rise above ambient of the hottest location on a FET divided by the power dissipated by the device shall be used as the thermal resistance u

26、nless failure analysis shows that the predominant failure location is elsewhere. This value averaged over the devices measured may be used for all devices and temperatures in the life test to convert between case and channel temperatures unless thermal resistance has been determined on 100% of the d

27、evices. Thermal resistance at a channel temperature of 140C +/-lPC shall also be determined on a sample so that results obtained later can be related to a case temperature. 4.2 Step Stress Tests If there are no data available on similar devices that can be used to determine the stress temperatures t

28、o be used, a step stress shall be performed. The step stress should use at least six devices, have the same bias and RF input power to be used in the life test, start at 150C baseplate temperature, proceed in steps of 25C of duration of at least 24 hours at each temperature, and with the electrical

29、measurements to be used in the life test made between every step. Similar step stress tests using constant temperature and increasing bias or RF input power may also be used to verify reasonable bias conditions for life testing. 43 Choice of Ambient Temperatares and Other Operating Contons The highe

30、st steady state stress temperature used shall be based on an expected median life of at least 100 hours; if too long an interval is used, the lowest temperature life test may take an unreasonable time or the life test temperatures may be too close together for a reasonable extrapolation. If the step

31、 stress test is used, the highest steady state stress baseplate temperature shali be at least 200C below the step stress baseplate temperature which produces 50% failure in 24 hours. In addition, if it is known that the dominant failure mechanism changes as the device temperature is raised above the

32、 temperature of application, the life tests shall be performed at temperatures below that transition temperature. There shali be at least three temperatures of steady state stress. The second shall be at least 15C below the highest, and the thud shall at least 15C below the second. In addition, if t

33、he lowest of the three baseplate temperatures is greater than 2WC, a fourth sample of devices shali be run at a baseplate temperature 50C above the device maximum operating temperature (or, if this is not specified, at a baseplate temperature of 15ooC) for a minimum of 2000 hours to verify the valid

34、ity of the extrapolation to the operation range. At this temperature, few failures are expected, and the analysis method of 4.9 could only state with high certainty that the median life is greater than 2000 hours. (A 2000 hour life at a channel temperature of 200C corresponds to 1 year at a device m

35、aximum operating temperature of 150C if the failure activation energy is 0.5 eV or 32 years if the failure activation energy is 2 eV.) Stresses other than temperature can also be performed for the purpose of determining acceleration factors. while they can not be expressed as activation energies, th

36、e dependence of device life on voltage, current, and other variables relevant to the device can be determined; the devices can be stressed above normal 0 _-_ _- EIA JEPLLB 93 W 3234600 0504104 184 JEDEC Publication No. 118 Page 4 operating conditions to accelerate the test. Analysis of the data is s

37、imilar to temperature dependence except that the functional dependence on each variable may be different. When using electrical overstress, the device temperature may change enough to impact device lifetime, and the ambient temperature of each electrical overstress group may have to be different to

38、keep the FET channel temperatures equal. 4.4 IaecmA stress During the step stress and life tests, the devices shall be operated under recommended dc operational electrical stress. If no recommended conditions exist, the bias conditions used shall be stated in the life test report. Unless special cir

39、cumstances prevail, low-noise and passive devices may be stressed with dc only, General purpose and power devices and MMICs not containing FETs shall be stressed with continuous wave RF. It is desirable that the RF stress level drive the device into at least 1 dB compression at the stress temperatur

40、e; the values of the RF input power, degree of compression, and frequency shall be stated in the life test report. If the life test is being run by or for a specific user, the operational dc and RF stress for the application shall be used. During the life tests, the devices shall be monitored period

41、ically to detect the occurrence of catastrophic failure and to adjust the equipment so that the applied stresses (temperature, current, voltage, etc.) are unchanged within tight tolerance except as described in the remainder of this section. Since the ideal life test is performed at constant tempera

42、ture and with constant electrical stresses, any drift in device performance prevents the ideal from being met. Engineering judgment shall be used to determine the best compromise in keeping the electrical stresses and the channel temperature of the devices on the baseplate constant, and gate voltage

43、 during stress shall be periodically adjusted as required to implement this compromise This compromise shall be described in the life test report, in order that the reader understands the life test conditions, and as a precedent for others facing the same problem in subsequent life tests. To facilit

44、ate failure analysis, the device stress circuitry should be designed to quickly remove voltage from the device once it has failed; this practice will minimize subsequent damage due to a runaway condition such as a shorted FET. 45 sample size A minimum sample size of 50 devim is recommended. This rep

45、resents the sum of all temperature groups which are taken to at least 70% failure. A larger sample size will provide more precise results in that the calculated confidence intervals wii be smaller. Allocation of the devices to the various stress temperatures is optimized by the technique of ref. 3 (

46、pp. 320 - 327). Since the lowest stress temperature (assumed greater than the operating temperature of interest) has the greatest impact in the extrapolation to the temperature of interest, more devices should be stressed at the lowest temperature than at the others. 4.6 Faiiure Criteria The failure

47、 criteria shall be expressed as a parametric change and shall be stated if different from those listed here. Unless stated otherwise, drain and gate voltages used in measurement shall be kept constant, allowing currents under measurement conditions to vary. Measurement temperature shall be consisten

48、t with 4.1. Changes defining failure: Current (operating or Iss) +/- 20% Switching time Insertion loss Phase error Other ELA JEPL38 93 W 3234600 0504305 O30 M JEDEC Publication No. 118 Page 5 as specified by manufacturer il- 20% +I- 1 dB +I- 20% of initial value (amplifiers only) - 1 dB (power devic

49、es only) +I- 0.5 dB (low-noise devices only) 3 dB change and less than 20 dB final isolation (switches only) + 100% (switches only) + 1 dB (switches only) +I- 11C (phase shifters only) as specified by manufacturer. i Gate bias current Transconductance RF small signal gain Power added efficiency Output power at 1 dB gain Noise figure Isolation - compression Operating current is defined as the current when the device is biased as it was at the start of the life test. Control devices shall be used to verify calibration of the measurement equipment. 4.7 Data Taking