1、EIMJEDEC PUBLICATION Guidelines for Preparing Customer-Supplied Background Information Relating to a Semiconductor-Device Failure Analysis EWJEP134 SEPTEMBER 1998 ELECTRONIC INDUSTRIES ALLIANCE JEDEC Solid State Technology Division Electronic Industries Alliance STD-EIA JEPL34-ENGL 1998 m 3234600 Ob
2、04323 T84 m NOTICE EWJEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. EINJEDEC standards and publications are designed to serve the public interest throu
3、gh eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be us
4、ed either domestically or internationally. EWJEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligatio
5、n whatever to parties adopting the EINJEDEC standards or publications. The information included in EWJEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization th
6、ere are procedures whereby a EINJEDEC standard or publication may be further processed and ultimately become an ANSIEL4 standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the
7、 content of this EWEDEC standard or publication should be addressed to JEDEC Solid State Technology Division, 2500 Wilson Boulevard, Arlington, VA 22201-3834, (703)907-75607559 or www.jedec.org. Published by ELECTRONIC INDUSTFUES ALLIANCE 1998 Engineering Department 2500 Wilson Boulevard Arlington,
8、VA 22201-3834 “Copyright“ does not apply to JEDEC member companies as they are free to duplicate this document in accordance with the latest revision of JEDEC Publication 21 “Manual of Organization and Procedure“. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards and Publicat
9、ions or call Global Engineering Documents, USA and Canada (1-800-854-7179, International (303-397-7956) Printed in the U.S.A. All rights reserved STD-EIA JEPL34-ENGL 1998 3234600 0604322 9LO JEDEC hblication No. 134 GUIDELINES FOR PREPARING CUSTOMER-SUPPLIED BACKGROUND INFORMATION RELATING TO A SEMI
10、CONDUCTOR-DEVICE FAILURE ANALYSIS CONTENTS Page 1 Introduction 2 Rationale 3 Purpose 4 Scope 5 Responsibilities 6 Terms and definitions 7 Description of Failure Analysis Request Form 8 Explanation of Failure Analysis Request Form 8.1 Requester?s tracking number 8.2 Requester 8.3 Technical contact 8.
11、4 Failed device description 8.5 Failed-device history 8.6 Failure-mode description 8.7 Additional information and comments 9 Applicable Documents ANNEX A - Sample Failure-Analysis Request Form 1 1 1 2 2 2 3 4 4 4 4 4 5 6 8 8 9 -1- STD.EIA JEPL34-ENGL L998 H 3234bOO Ob04323 857 m JEDEC Publication No
12、. 134 Page 1 GUIDELINES FOR PREPARING CUSTOMER-SUPPLIED BACKGROUND INFORMATION RELATING TO A SEMICONDUCTOR-DEVICE FAILURE ANALYSIS (From JEDEC Council Ballot JCB-98-14, formulated under the cognizance of the JC-14.6 Subcommittee on Failure Analysis.) 1 Introduction This Guideline addresses acquiring
13、 and transmitting pertinent background information that a failure analyst should have to complete an accurate and timely failure analysis of a semiconductor device. To this end, a suggested background-data form and explanations of its data items are included. 2 Rationale The electronic-equipment man
14、ufacturing industry is demanding ever shorter failure-analysis laboratory turnaround times. To meet this demand, failure analysts are trying to expedite the analysis process; however, to make correct decisions, the failure analyst should understand the requesters manufacturing processes, should know
15、 about deviations from normal operating conditions, and should be aware of problems observed near the time of failure. Lack of this key background information frequently forces the failure analyst to contact the requesters technical person, and this additional research effort delays initiation of th
16、e failure analysis, resulting in longer-than-necessary laboratory turnaround time. This Guideline offers a convenient Failure-Analysis Request form that provides a vehicle for acquiring and transmitting the desired information in a concise, organized, and consistent format. While all of the informat
17、ion requested in the aforementioned form may not be applicable or available, the form does facilitate transferring the maximum amount of background data to the failure analyst in a readily interpretable format, and immediate availability of this key information assists the analyst in completing a ti
18、mely and accurate failure analysis. 3 Purpose The purpose of this Guideline is to establish a uniform mechanism for transmitting background data on a suspected component failure to the failure analyst so that laboratory turnaround time can be reduced and probability for successful failure resolution
19、 can be improved. STD=EIA JEPL34-ENGL 1998 = 3234600 Ob04324 793 JEDEC Publication No. 134 Page 2 4 Scope This Guideline presents a suggested Failure-Analysis Request form for transmitting background information that is essential for accurate and timely completion of a failure analysis. Included als
20、o are explanations of terms used on the form. The sample Failure-Analysis Request form appended to this Guideline is quite general; that is, it applies to both semiconductor-device fabrication facilities as well as to manufacturers of printed-wiring boards and complete electronic systems. 5 Responsi
21、bilities To facilitate transmission of the desired background information, the requester of a failure analysis should assume responsibility for initiating entry of the requested information on the Failure-Analysis Request form and transferring the completed form to the next person in the protocol ch
22、ain. Each person who receives the completed form should assume responsibility for transmitting it to the next person in the chain until the form ultimately reaches the failure analyst. The failure analyst then should reciprocate by completing a timely and accurate failure analysis and starting a fai
23、lure-analysis report through the reverse protocol chain. 6 Terms and definitions failure analysis: A methodical process of testing, dissecting, and inspecting a semiconductor device that is suspected of malfunctioning with the goals of locating the failure site and determining the cause of failure.
24、failure analyst: A person, employed by either the manufacturer of the failed device or an independent laboratory, skilled in failure analysis of semiconductor devices. failure-analysis laboratory turnaround time: The time period beginning with receipt in the failure-analysis laboratory of a failed d
25、evice and associated background information and ending with submission of a failure-analysis report and closure with the customer. requester: The person, employed by either the organization that uses the component in question (i.e., the customer) or the device manufacturer (e.g., in wafer fabricatio
26、n), who initiates the request for a failure analysis. * catastrophic failure: A failure that has serious consequences for the failed device or other components associated with it in the circuit (e.g., input shorted to power supply or ground, power-supply-to-ground short circuit, destructive latchup,
27、 etc.) STDmEIA JEP134-ENGL 1998 m 3234600 Ob04325 b2T m JEDEC hblication No. 134 Page 3 6 Terms and defmitions (contd) functional failure: Failure of a device to deliver correct output data or signals during operation (e.g., stuck-high or -low output, open input or output, logic error, etc.). parame
28、tric failure: Out-of-tolerance current or voltage level at an input, output, or power- supply terminal of a component; parametric failures are usually detected during input-leakage, output-voltage, and power-supply-current tests. programming failure: Failure of a nonvolatile memory device, such as a
29、 programmable read- only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), etc., to respond properly during a write andor read test. timing failure: Operational malfunction caused by propagation delays, read/write times, rise
30、 and fall times, setup times, etc. that do not meet device specifications. 7 Description of Failure Analysis Request Form The sample Failure-Analysis Request form presented in the Annex A is intended to serve as a vehicle for organizing and transmitting background information that is essential to th
31、e failure analyst if an accurate and timely analysis is to be performed. This sample form is of a general nature, so it includes items that pertain specifically to the device-fabrication process and other items that relate to the device-users processes for assembling printed-wiring boards and find p
32、roducts. Thus, the form includes items that may not be relevant to a particular device manufacturers products, and some product-specific items that are important to a device manufacturer may have been omitted. Therefore, it is permissible for a device manufacturer to modify the form to eliminate irr
33、elevant items and to add relevant items; however, it is strongly recommended that general structure, organization, and wording of the sample form be maintained in the modified version so that all personnel involved in component failure analyses can readily comprehend the needs for information and im
34、mediately understand the transmitted data. The Failure-Analysis Request form, as embodied in the appended sample, is divided into sections. At the top of each page is a header in which the failure-analysis laboratory is identified; this header may be altered to accommodate company policy, but as a m
35、inimum it should include the name and location of the company that operates the failure-analysis laboratory. Logotypes, business addresses, telephone and fax numbers, e-mail addresses, etc. may be included optionally. JEDEC Publication No. 134 Page 4 7 Description of Failure Analysis Request Form (c
36、ontd) Remaining sections of the sample form provide spaces for entering detailed information about personnel requesting the failure analysis, description, history, and failure symptoms related to the failed device, and additional information and comments that may assist the failure analyst. In most
37、of these sections, there are specific questions that should be answered as completely as possible if a satisfactory failure analysis and a short laboratory turnaround time are expected. 8 Explanation of items on Failure Analysis Request Form Terminology used in each section of the sample Failure-Ana
38、lysis Request form (Annex A) is explained in this section of this Guideline. Items are addressed in the order that they appear on the sample form. 8.1 Requesters tracking number The Requesters tracking number is assigned by the requester for purposes of associating information entered in the Failure
39、-Analysis Request form (Annex A) with related data and records held by the requesters organization. 8.2 Requester The requester is the person, employed by either the organization that uses the component in question (i.e., the customer) or the device manufacturer (e.g., in wafer fabrication), who ini
40、tiates the request for a failure analysis; this person should provide information needed to fill in the relevant lines in the Requester box on the form. 8.3 Technical contact The technical contact is a person who has first-hand technical knowledge of the failure, including conditions existing just p
41、rior to failure and conditions under which the failure was detected. Because it may be necessary for the failure analyst to contact this person for additional information or clarification, this person should completely fill in the relevant lines in the Technical Contact box on the form. 8.4 Failed-d
42、evice description Markings on the failed-device package should be recorded in this section of the form. Additional items that may not be included in the device markings are also desired; these include the date code for the lot from which the failed device came, the device-manufacturers part number,
43、the device-manufacturers lot number, the requesters part number, and the quantity of devices submitted for failure analysis. STD-EIA JEPL34-ENGL 1998 m 3234600 0604327 4T2 m JEDEC Publication No. 134 Page 5 8 Explanation of items on Failure Analysis Request Form (contd) 8.5 Failed-device history Ass
44、essment of device history is a very important part of the failure-analysis process. Because information entered in this section is especially important, items are described on a line-by-line basis. Where were devices purchased? When? On this line, the users (Le., requesters) source of the failed par
45、ts and the date of purchase are requested. Possible sources include, for example, the device manufacturers sales organization or a local or national distributor. Lot quantities: Information that should be entered on this line includes (1) the number of units in the originally purchased lot of device
46、s, (2) the quantity from this lot that was tested or inspected, and (3) the quantity of tested or inspected devices in which the suspected failure mode was detected. Were devices subjected to any value-added processing? . For purposes of this question, value-added processing includes such operations
47、 as bum-in, screening (e.g., for specific ranges of electrical parameters), lead forming, environmental testing (i.e., environmental stress screening), incorporation of the parts in a subassembly, etc. A “yes or no“ answer is desired. If value-added processing was performed, then names and addresses
48、 of providers of these services should be included, and the types of processing performed should be described fully. Specifications and drawings are useful supplements to the description placed on the form. Where in the process was failure discovered? . The appropriate box in this section should be
49、checked, or if the listed items are not relevant, then the Other space should be used to describe the point in the process at which failure was detected. Note that the process points listed on the sample form cover semiconductor-device fabrication as well as user product-manufacturing process steps. What was the last assembly step before failure was discovered? Within each of the major process steps associated with the previous question, there may be numerous substeps; it is the specific substep at which failure was detected that is requested in answer to thi
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