JEDEC JEP150 01-2013 Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Components (Minor revision of JEP150 May 2005 Re.pdf

1、JEDEC PUBLICATION Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Components JEP150.01 (Minor revision of JEP150, May 2005, Reaffirmed JUNE 2011) JUNE 2013 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications

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9、e reproduced without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Publication No. 150 -i- Stress-Test-Driven Qualificatio

10、n of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Components Introduction The present solid state component level qualification procedures do not always ensure that the packaged component will operate reliably after assembly on printed wire boards (PWBs), or the like, s

11、ince the free standing device level qualification may not induce the same thermomechanical stresses present in the post second level assembly state. As component interconnections decrease in size, e.g., the component is closer to the PWB; the interaction of the second level assembly becomes increasi

12、ngly more likely on the components performance. This document demonstrates how to evaluate the effect of assembly level operations and structures on components. As such, this document pertains predominantly to the following set of solid state devices and component packages that are described in the

13、Scope. Knowledge of and comparison with packaged component failure mechanisms and modes is needed between the free standing and the assembled state. To ensure an effective qualification methodology for this set of solid state surface-mounted components, testing shall be performed in both the free st

14、anding and assembled state, including attached heat sinks where applicable. It should be noted that peripheral leaded surface-mount components are not considered in this document because, in general, the thermomechanical stresses imparted to the component in its assembled state are minimal, due to t

15、he inherent flexibility of their leads. JEDEC Publication No. 150 -ii- JEDEC Publication No. 150 Page Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Components (From JEDEC Board Ballot, JCB-05-56, formulated under the cognizance of the

16、JC-14.3 Subcommittee on Silicon Devices Reliability Qualification and Monitoring.) 1 Scope This publication contains a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as ind

17、ividual solid state surface-mount products, in particular leadless chip carriers, ball grid array (BGA) packages, direct chip attach die and packages with exposed pads that are attached to the PWB for thermal considerations. Assembly level testing may not be a prerequisite for device qualification;

18、however, if the effect of assembly conditions on the component is not known, there could be reliability concerns for that component that are not evident in component level testing. As such, it is recommended that assembly level testing be performed to determine if there are any adverse effects on th

19、at component due to its assembly to a PWB. These reliability stress tests have been found capable of stimulating and precipitating failures in assembled components in an accelerated manner, but these tests should not be used indiscriminately. Each qualification should be examined for: a) Any potenti

20、al new and unique failure mechanisms. b) Any situation where these tests and/or conditions may induce false failures. In either case the set of reliability requirements, tests and/or conditions should be appropriately modified to properly comprehend the new situations. This document does not relieve

21、 the supplier of the responsibility to meet internal or customer specified qualification programs. 2 Terms and definitions second level assembly: The attachment of a component to the next level of assembly packaging. packaged device: A semiconductor device within an enclosure that allows electrical

22、connection to and provides mechanical and environmental protection for that device. free-standing state (of a component): The state of a component that is not attached to the next level of assembly packaging. assembled state (of a component): The state of a component that has been attached to a seco

23、nd level assembly. JEDEC Publication No. 150 Page 2 Terms and definitions (contd) chip package interaction (CPI): The interaction between the semiconductor package stresses and the semiconductor device. peripheral-leaded surface-mount component: A component with a metal frame that provides external

24、surface-mountable terminals located around the periphery of the body of the component. 3 Reference Documents JEP122, “Failure Mechanisms and Models for Silicon Semiconductor Devices” JESD74, “Early Life Failure Rate Calculation Procedure for Electronic Components” JESD85, “Calculation of Failure Rat

25、e in Units of FITs” JESD9, “Method for Developing Acceleration Models for Electronic Component Failure Mechanisms” JESD94, “Application Specific Qualification using Knowledge Based Test Methodology” JESD22, “Reliability Test Methods for Packaged Devices” JEP131, “Process Failure Modes and Effect Ana

26、lysis (FMEA)” JESD47, “Failure Mechanisms and Models for Silicon Semiconductor Devices” IPC/JEDEC 9702, “Monotonic Bend Characterization of Board-Level Interconnects” IPC 9701, “Solder Joint Reliability Test Method” SEMATECH White Paper #99083810A-XFR, “Use Condition Based Reliability Evaluation of

27、New Semiconductor Technologies” SEMATECH White Paper #99083813A-XFR, “Use Condition Based Reliability Evaluation: An Example Applied to Ball Grid Array (BGA) Packages” 4 Understanding stress interactions The apparent stresses and distribution of stresses imparted to the solid state component during

28、free-standing component qualification testing may not match the actual stresses and associated distribution that the component will be subjected to when surface mounted on a printed wiring board (PWB). Failure modes may also be different. Figure 1 shows the various interactions that exist between th

29、e packaged device and its free-standing and assembled state that can affect the components reliability in the final field application. Area 1 in Figure 1 refers to the reliability of the free-standing component prior to assembly to a PWB. Qualification procedures have been established for components

30、, see JESD47 (Stress Test Driven Methodology) and JESD94 (Application Specific Qualification using Knowledge Based Test Methodology). JEDEC Publication No. 150Page 4 Understanding stress interactions (contd) ComponentBoardBoard Assembly1A) Effect of assembly on component3) 2nd Level Interconnect2A)

31、Effect of assembly on Board1) Base Component Reliability2) Base Board ReliabilityFigure 1 Levels of Assembly - Interaction of packaging technical concerns When the component is assembled onto a printed wiring board (PWB), or the like, the assembly process can affect the reliability of the component

32、by exposing it to new or altered assembly related stress levels and stress distributions as shown in area 1A of Figure 1. This is the primary focus in this document. The major concern is that the component, as assembled, will exhibit failure modes that were not detected during the qualification of t

33、he free-standing component. Failures can be found in the various areas of the component including the package materials, package circuitry and the silicon device due to chip to package interactions. Example: A specific example of this is beam lead failures seen in micro BGA packages. The micro BGA p

34、ackage typically uses a highly compliant and low modulus elastomer to de-couple the die from the flex tape. Failures are generally not seen during the component level qualification. However, when the package is assembled on the next level, there is a shift in the composite coefficient of thermal exp

35、ansion (CTE) of the assembled component. This mismatch drives stresses from the solder joints to the copper beam leads inside the package. This may result in beam lead failures, which can be detected during thermal cycling tests of the assembled component. Area 2 in Figure 1 refers to the reliabilit

36、y of the PWB. PWB stand-alone reliability testing is not addressed in this document. Area 3 is the interconnection between the component and the PWB, also referred to as the second level interconnect. It will be addressed in this document, only as it relates to the reliability of the component, incl

37、uding its solder interconnection members, e. g., BGA, flip chip, or LCC solder joints. Items associated with the PWB and their affect on the PWB solder interconnection are not being covered in the assembly test sequence, including PWB surface contamination, insufficient cleaning of trapped fluxes or

38、 improper handling of the PWB assembly that cause PWB failure. JEDEC Publication No. 150 Page 5 Determining second level test requirements One should examine the suggested tests, failure mechanisms and failure modes associated with component level qualification and compare them to those associated w

39、ith assembly level qualification. By examining the failure modes in the assembly level qualification, that are not detected during component level qualification, it is possible to specify the assembly level tests that should be used in conjunction with the component level tests. This will better ens

40、ure that the qualification procedure used can detect all known failure modes and mechanisms for a component in its projected use. Each qualification project should be examined for (a) any potential new and unique failure mechanisms and (b) any situations where the standardized tests and conditions m

41、ay induce failures not relevant in the field. Use of both historical knowledge information and failure modes and effect analysis (FMEA) is a means that can be used to improve the qualification process test sequence selection. Annex A provides a fairly extensive list of various failure mechanisms for

42、 components in the free standing and assembled condition and it gives a brief description of their relationship to accelerated tests. Though extensive, this list should not be assumed to be complete. With new materials and processes, new failure mechanisms continue to be found. Annex A should help f

43、acilitate the process of identifying potential failure mechanisms and the determination of an appropriate qualification strategy and plan. It can be used in conjunction with Table 2 where the same failure mechanisms are listed with the corresponding reliability stress test(s) that can be used to rev

44、eal reliability problems. 6 Component level/ second level assembly qualification tests Table 1 shows a comparison between the tests and conditions used to evaluate and qualify free-standing components versus the tests and conditions used to evaluate and qualify components assembled to PWB, or the li

45、ke. It is only to be used as a general comparison between the testing performed on free-standing versus assembled components. It is not intended to be used as a list of required stresses. Dependent on the specific application, other tests or combination of tests may be appropriate. This must be eval

46、uated on a case-by-case basis. Note that sequential and simultaneous environmental testing has been used where appropriate, per reference. 7 Comparison of qualification methodologies A component and assembly level test selection guideline for the various reliability failure mechanisms, listed in Ann

47、ex A, is provided in Table 2. The failure modes listed are typical, but with ever changing material sets, device construction and assembly conditions the list in Table 2 is not guaranteed to be complete and must be considered strictly as a guide. Tests performed at component and assembly level are d

48、esignated “C” and “A”, respectively. Failure mechanisms that are found in both component and assembly level tests, but shift either in time to failure or location of failure, are denoted by “M” for a failure mode shift. Table 2 provides a reference as to which stress tests can be used to uncover the

49、 particular failure mechanism. It should be used as a guideline only. JEDEC Publication No. 150 Page 7 Comparison of qualification methodologies (contd) Table 1 Typical JEDEC Stress Tests For Component 2- Ball size, standoff and composition; 3- PWB thickness, x-section, CTE (X, Y, Z), warpage and PTH pattern; 4- Assembly configuration, including near neighbor components, single versus double sided (with shared via) and heat sink size and attachment method; and 5- Assembly attributes including past