JEDEC JEP159A-2015 Procedure for the Evaluation of Low-k Metal Inter Intra-Level Dielectric Integrity.pdf

1、JEDEC PUBLICATION Procedure for the Evaluation of Low-k/Metal Inter/Intra-Level Dielectric Integrity JEP159A (Revision of JEP159, August 2010) JULY 2015 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved th

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9、olid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Publication No. 159A -i- PROCEDURE FOR THE EVALUATION OF LOW-K/METAL INTER/INTRA-LEVEL DIELECTRIC INTEGRITY Contents Page

10、 Foreword ii Introduction ii 1 Scope 1 2 Terms and definitions 2 2.1 Abbreviations 2 2.2 Symbols 2 3 Test Structure Overview 4 4 VRDB Test Overview 6 4.1 Pre-VRDB Test 6 4.2 VRDB Test 6 4.2.1 Dielectric Breakdown Criteria 7 4.2.1.1 Absolute Current Level 8 4.2.1.2 Slope change Breakdown criteria 8 4

11、.3 Post-VRDB Dielectric Current Test 9 4.4 Data Recording 9 4.5 VRDB Data Analysis 9 5 CVS Stress Overview 10 5.1 CVS Test 10 5.2 Test procedure 11 5.2.1 Pre-CVS Test 11 5.2.2 CVS Stress Test 11 5.2.3 Post-CVS Test 11 5.3 Data Recording 12 5.4 TDDB Data Analysis 12 6 References 12 Annex A (informati

12、ve) Supplemental data analysis 13 A.1 Determination of ILD Electric Field 13 A.2 Acceleration Models 13 A.2.1 Field Extrapolation Models 13 A.2.2 Thermal Acceleration Models 14 A.2.3 Area Scaling Model 14 A.2.4 Determining Failure Rate 14 A.2.5 Sample Size 15 A.2.6 TDDB Distribution 15 A.2.7 In-die

13、Weibull Slope Determination and Data Deconvolution 15 Annex B (informative) Differences between JEP159A and JEP159 21 JEDEC Publication No. 159A -ii- Foreword This document is intended for use in the semiconductor IC manufacturing industry and provides reliability characterization techniques for low

14、-k inter/intra level dielectrics (ILD) for the evaluation and control of ILD processes. It describes procedures developed for estimating the general integrity of back-end-of-line (BEOL) ILD. Two basic test procedures are described, the Voltage-Ramp Dielectric Breakdown (VRDB) test, and the Constant

15、Voltage Time-Dependent Dielectric Breakdown stress (CVS). Each test is designed for different reliability and process evaluation purposes. This document also describes robust techniques to detect breakdown and TDDB data analysis. Introduction Two test procedures are described within this document: a

16、 fast VRDB test, and a constant voltage TDDB test (CVS). Each of these procedures is designed for different evaluation purposes and can be implemented separately or complementally. The VRDB test starts at zero voltage or Vuseand ramps linearly until dielectric breakdown occurs and can be conducted a

17、t either room temperature or at higher temperatures to accelerate the occurrence of the degradation mechanism to failure. VRDB tests are important to characterize the defects at lower electrics fields and the dielectric breakdown strength of dielectric for a given process. The CVS test starts at a f

18、ixed voltage and is kept at this fixed voltage until dielectric breakdown occurs. The test can also be performed at higher temperatures to accelerate failure. TDDB tests are important to characterize the long-term dielectric acceleration parameters and to calculate the ILD based fraction of the fail

19、ure rate or lifetime of a product. JEDEC Publication No. 159A Page 1 PROCEDURE FOR THE EVALUATION OF LOW-K/METAL INTER/INTRA-LEVEL DIELECTRIC INTEGRITY (From JEDEC Board Ballot JCB-15-23, formulated under the cognizance of JC-14.2 Subcommittee on Wafer Level Reliability.) 1 Scope The continued scali

20、ng of advanced VLSI circuits, particularly of high performance logic circuits, is driving the need for low-k materials and copper metallization in back end of the line (BEOL) interconnect systems to reduce the resistance-capacitance (RC) delay, cross talk noise, and power dissipation. With the wide

21、applications of low-k and ultra-low-k dielectric materials at the 90nm technology node and beyond, the long-term reliability of such materials is rapidly becoming one of the most critical challenges for technology qualification. Low-k time dependent dielectric breakdown (TDDB) is commonly considered

22、 as an important reliability issue because low-k materials generally have weaker intrinsic breakdown strength than traditional SiO2dielectrics. This problem is further exacerbated by the aggressive shrinking of the interconnect pitch size due to continuous technology scaling. The procedures outlined

23、 herein were developed to estimate the electrical breakdown performance of low-k ILD and as a tool for driving constant improvement in the low-k ILD process. The test procedure described within this document should be used as common methodology for low-k ILD process control and improvement and could

24、 be used as a guideline to predict the effect of ILD TDDB on product lifetime or failure rate. In actual practice the ILD TDDB reliability of a semiconductor product is a complicated function of the interconnect critical area, power duty cycles, transient voltage variation, and series resistance. Th

25、ese parameters are not considered within this document. The purpose of this document is to describe test procedures for characterizing the reliability of inter/intra level dielectrics. It does not specify acceptance or rejection criteria for any of the described procedures. JEDEC Publication No. 159

26、A Page 2 2 Terms and definitions The following abbreviations and symbols are used in this document. They have been listed alphabetically for the convenience of the reader. 2.1 Abbreviations BEOL: Back end of line CVS: Constant voltage stress DUT: Device under test ILD: Intralevel and/or interlevel d

27、ielectric MLE: Maximum likelihood estimation TDDB: Time dependent dielectric breakdown VRDB: Voltage ramp dielectric breakdown 2.2 Symbols AILD(cm2): Total active area of dielectric. EILD(V/cm): The ILD electric field. The general formula for E is: EILD= VILD/ SILD, (1) where VILDis the ILD voltage

28、and SILDis the physical ILD spacing between two metal lines. SILDmust be determined by a consistent, documented method. The method of determining SILDor a reference to the documented standard must be included in the data report. Ebd (V/cm): The estimated ILD electric field just before ILD breakdown.

29、 Ibd(A): ILD current measured just before ILD breakdown. Icomp (A): The maximum current of the voltage forcing equipment. Often the user can specify a compliance limit for a particular test. Iinit(A): ILD failure current when Vuseis applied. This value is determined as a deviation from typical curre

30、nt vs. voltage characteristics measured from good devices. For maximum sensitivity the value should be well above the worst case ILD leakage current of a “good” ILD and at least 10 times greater than the noise floor of the test systems. A recommended value is 50 times the measured value for a good s

31、tructure. Or a pre-defined absolute leakage level such as 100nA, which could critically affect chip performance and cause chip operation failure, could be used as failure criterion. Imeas(A): The measured ILD current. JEDEC Publication No. 159A Page 3 2.2 Symbols (contd) Iuse(A): The typical measure

32、d current through the ILD at the normal use voltage. Istress(A): The ILD current measured during the CVS test. Iprevious(A): The previously measured ILD current. Istress-t0(A): The initial dielectric current measured at Vstressduring the CVS test. tbd(s): The recorded time at ILD failure. tint(s): T

33、he time interval to sense ILD current during the CVS test. This value should be Iinit, record as initial failure 5) Repeat for all available DUTs on wafer 4.2 VRDB test A linear or stepped voltage ramp is applied to the dielectric test structure. The voltage starts at zero voltage or the use voltage

34、 Vuse, and ramps at a predefined ramp rate, or is stepped by the voltage, Vstep, for a duration tstep. During the voltage ramp, the current is monitored as least as often as tstep. For the stepped voltage ramp, the current measurement should be delayed at each voltage step to allow displacement curr

35、ents to settle. This indicates that tstepmust be longer than the instruments settling time plus the measurement time of the test system. JEDEC Publication No. 159A Page 7 4.2 VRDB test (contd) Table 1 Recommended values for the VRDB and CVS tests Parameter Units Comments Kslope Slope increase factor

36、 when comparing subsequent slopes during the VRDB tests. Kslopecan vary between 3 and 10. See 4.2.1.2 Iinit A ILD breakdown failure current when Vuseis applied. This value is determined as a deviation from typical current vs. voltage characteristics measured from good devices. For maximum sensitivit

37、y the value should be well above the worst case ILD leakage current of a “good” ILD and at least 10 times greater than the noise floor of the test systems. A recommended value is 50 times the anticipated value for a good structure. Or a pre-defined absolute leakage level such as 100 nA, which could

38、critically affect chip performance and cause chip operation failure, could be used as failure criterion. Iuse A ILD current measured when Vuseis applied during the pre-ramp test. This current density should be at least 10 times greater than the noise floor of the test system. Ramp rate MV/cms The ra

39、mp rate is specified at 1 MV/cms tint s Interval time to sense ILD current during the CVS test. This value should be 10 X Iuse). This level must be carefully selected by measuring IV curves from representative samples as huge variations of ILD leakage and breakdown voltage are expected for test stru

40、ctures with different design geometries, at different metal levels, and with different process splits. Therefore, the criteria should be carefully selected to assure a real catastrophic ILD breakdown detection. This method is not suitable for ILD breakdown exhibiting an “open” signature instead of a

41、 “short” due to metal damage caused by extremely high transient discharge current during the breakdown event. 4.2.1.2 Slope change of dielectric current versus voltage An abrupt current increase This criteria specifies that dielectric breakdown occurs when the logarithmic slope of Imeasvs. Vstresscu

42、rve continuously increases by a slope increase factor (Kslope) greater than the previously calculated slope with at least four points and three slope comparisons. The previous logarithmic slope (Slope1) is calculated from ()() ()()21211=nnnnVVIAbsLnIAbsLnAbsSlopewhere In-1, Vn-1,In-2,and Vn-2are the

43、 measured currents and voltages of the previous two data points, respectively. The new slope (Slope2) is calculated using ()() ()()112=nnnnVVIAbsLnIAbsLnAbsSlopewhere In, Vn,In-1,and Vn-1are the measured currents and voltages of the second most recent and previous data points, respectively. The thir

44、d slope (Slope3) is further calculated to verify true slope increase ()() ()()nnnnVVIAbsLnIAbsLnAbsSlope=+113where In, Vn,In-1,and Vn-1are the measured currents and voltages of the most recent and previous data points, respectively. If slope3 Kslope X (slope2) Kslope X (slope1) then the test should

45、be terminated and the device is considered to be broken down. Kslope can have a value between 3 and 10 and can be varied for actual hard breakdown events depending on device area, ILD thickness, structure layout, or process. Voltage-to-breakdown, Vbdis defined as Vn. This method is suitable for dete

46、cting both “short” and “open” breakdowns. JEDEC Publication No. 159A Page 9 4.3 Post-VRDB dielectric current test Once the voltage ramp is completed, following the detection of breakdown defined in 4.2.1, a post-ramp current test with Vuse applied to the metal interconnect is used to determine the f

47、inal state of the tested device. Hard breakdown is attributed to all the devices with post-VRDB Iuse-post Iinitand is classified as a valid failure. If Iuse-post= .9 Vmaxthen the device has broken down, but is open circuited and is classified is a valid failure. During the breakdown event, extremely

48、 high transient currents flow. Such large discharge current comes from the charge stored in the test structure. The greater the local dielectric voltage, the greater the energy released into the breakdown electrodes. Peak discharge currents may occur during the ILD rupture event caused by voltage ra

49、mping. This high peak current could destroy metal to form open circuits or burn-out contacts. Therefore, a false “open” event instead of “short” could be detected by the instrument. As those “opens” are indeed induced by first electrical “shorts”, and the time interval between “short” and “open” is very short, the voltage at the onset of “open” could be treated as the breakdown voltage. An invalid breakdown would indicate a potential problem with the test fixture setup or with the instrumentation. 4.4 Data recording For VRDB test, the following information should be