JEDEC JEP160-2011 Long-Term Storage for Electronic Solid-State Wafers Dice and Devices.pdf

1、JEDEC PUBLICATION Long-Term Storage for Electronic Solid-State Wafers, Dice, and Devices JEP160 NOVEMBER 2011 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level an

2、d subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purch

3、aser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents

4、 or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach

5、to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with th

6、is standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternativ

7、e contact information. Published by JEDEC Solid State Technology Association 2011 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not t

8、o charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies

9、through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards and Documents for alternative contact information. JEDEC Publication No. 160 -i- LON

10、G-TERM STORAGE GUIDELINES FOR ELECTRONIC SOLID-STATE WAFERS, DICE, AND DEVICES Introduction Age does not adversely affect solid-state electrical performance provided no degradation in materials occurs. This publication provides the industry with the best practices and recommendations for packing and

11、 storing solid-state electronics for long-term storage (LTS). For the purposes of this document, LTS is defined as continuous storage where J-STD-033 does not apply. JEDEC Publication No. 160 -ii- JEDEC Publication No. 160 Page 1 LONG-TERM STORAGE GUIDELINES FOR ELECTRONIC SOLID-STATE WAFERS, DICE,

12、AND DEVICES (From JEDEC Board Ballot JCB-11-77, formulated under the cognizance of the JC-14.3 Subcommittee on Silicon Devices Reliability Qualification and Monitoring.) 1 Scope This publication examines the LTS requirements of wafers, dice, and packaged solid-state devices. (Note: Packaging may inc

13、lude encapsulation, under-fill, over-mold, or other techniques to attach a die to the next level of assembly.) The user should evaluate and choose the best practices to ensure their product will maintain as-received device integrity and minimize age- and storage-related degradation effects. Major de

14、gradation concerns can be driven by moisture-induced corrosion, contamination, electrostatic fields, temperature effects, and outgassing. Please refer to J-STD-033 for non-LTS criteria as well as requirements for moisture sensitivity levels, environmental conditions, dry bag requirements, handling,

15、shipping, and desiccant calculations. Wafers and dice that are in process or finished may require LTS depending upon program needs. Environmental factors should be evaluated to avoid electrostatic discharge (ESD) damage and to protect the wafer and die bond pads and the device terminal leads against

16、 corrosion and damage until any die is packaged or otherwise attached in its next level of assembly. Specific ESD requirements and procedures can be found in ANSI/ESD S20.20, EOS/ESD S8.1, and JESD625 as applicable. Solid-state devices may be constructed from either organic or ceramic materials. Man

17、y organic packaged solid-state devices are designed to attach the semiconductor die to copper die bond pads or heat spreaders or stiffeners. These packages utilize organic resins and other carbon-based materials which can absorb and retain moisture, leading to failure mechanisms such as delamination

18、, corrosion, and warpage. Ceramic solid-state devices are constructed from inorganic materials such as alumina or glass frit. Ceramic devices can develop corrosion from moisture exposure. Ceramic devices can be damaged from handling. Effective use of this publication is intended to prevent environme

19、ntal damage to and maintain reliability of wafers, dice and unassembled solid-state devices during LTS. Product destined for LTS should be free from any initial storage concerns, including contamination from process chemicals, fluxes, handling damage, etc. LTS product should be inspected prior to us

20、e to ensure no detrimental effects. Metallic whiskers (such as tin, silver, copper) could develop depending upon moisture and temperature environmental conditions. This document does not relieve the supplier of the responsibility to meet internal or customer specified requirements or qualification p

21、rograms. JEDEC Publication No. 160 Page 2 2 Terms and Definitions critical moisture limit: The maximum safe equilibrium moisture content for a specific encapsulated device at reflow assembly or rework. interlevel dielectric (ILD): The dielectric material used to electrically separate closely spaced

22、interconnect lines arranged in several levels (multilevel metallization) in an advanced integrated circuit long-term storage (LTS) : Uninterrupted storage where the conditions and requirements of J-STD-033 do not otherwise apply; e.g., safe storage, shelf life, floor life. NOTE Allowable storage dur

23、ations will vary by form factor (e.g., packing materials, shape) and storage conditions. In general, long-term storage is greater than one year. LTS packaged hardware: The wafers, dice, or encapsulated devices that have additional packaging for storage to protect from moisture and mechanical impact

24、and for ease of identification and handling. LTS storeroom: An area containing wafers, dice, or packaged devices that have additional packaging for storage to protect from moisture or from mechanical impact or for ease of identification or handling. moisture-sensitive device (MSD): Any device that e

25、xhibits moisture absorption or moisture retention and whose quality or reliability is affected by moisture. next-level assembly: The attachment of a die or packaged device to the next level of assembly packaging. printed circuit board (PCB): A substrate used to mechanically support and electrically

26、connect electronic components using conductive pathways or signal traces by printing or etching tracks of a conductor such as copper on one or both sides of an insulating substrate. NOTE A PCB is also called a printed wiring board (PWB) or etched wiring board. under-bump metallization (UBM): A patte

27、rned, thin-film stack of material that provides 1) an electrical connection from the silicon die to a solder bump; 2) a barrier function to limit unwanted diffusion from the bump to the silicon die; and 3) a mechanical interconnection of the solder bump to the die through adhesion to the die passiva

28、tion and attachment to a solder bump pad. under-bump metallurgy (UBM): The metal layers located between the solder bump and the die. JEDEC Publication No. 160 Page 3 3 References and Other Useful Resources 3.1 IPC1/ JEDEC2IPC-T-50, Terms and Definitions for Interconnecting and Packaging Electronic C

29、ircuits. JESD88, Dictionary of Terms for Solid State Technology. IPC/JEDEC J-STD-033, Handling, Packing, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices. JESD201, Environmental Acceptance Requirements for Tin Whisker Susceptibility of Tin and Tin Alloy Surface Finishes. JESD625,

30、Requirements for Handling Electrostatic Discharge Sensitive (ESD) Devices. JEP113, Symbol and Labels for Moisture-Sensitive Devices. IPC/JEDEC J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices. IPC-1601, Printed Board Handling and Storage Guideli

31、nes. 3.2 ANSI3ANSI/ESD S20.20, Protection of Electrical and Electronic Parts, Assemblies and Equipment (Excluding Electrically Initiated Explosive Devices). 3.3 Electrostatic Discharge Association (ESD)4EOS/ESD S8.1, Protection of Electrostatic Discharge Susceptible Items - Symbols - ESD Awareness.

32、3.4 Military Standards5MIL-PRF-81705, Performance Specification Barrier Materials, Flexible, Electrostatic Protective. MIL-PRF-131H, Barrier Materials. 3.5 ISO6ISO 14644, Cleanrooms and Associated Controlled Environments. 3.6 ASTM7ASTM D3330, Standard Test Method for Peel Adhesion of Pressure-Sensit

33、ive Tape. _ 1. www.ipc.org 2. www.jedec.org 3. www.ansi.org 4. www.esda.org 5. www.dscc.dla.mil/Programs/MilSpec 6. www.iso.org 7. www.astm.org JEDEC Publication No. 160 Page 4 4 LTS Control The following recommendations are best practices when storing wafers, dice, or solid-state devices. This guid

34、eline does not preclude the use of specialized tools or equipment or alternative storage practices (e.g., use of moisture regulators, electrostatic discharge protection systems, etc.) for LTS control. Alternative practices should be evaluated and documented to ensure conformance to product requireme

35、nts and LTS criteria. 4.1 Materials Packing materials that deteriorate with age should not be used since outgassing of chemicals and decomposition products could contaminate the product. Use of specific materials for LTS should be identified and utilized (e.g., closed-cell foams with nitrogen fillin

36、g). 4.1.1 Moisture Barrier Bag (MBB) Refer to J-STD-033. Utilization of MBBs for LTS is not limited to MSD hardware. The use of MBBs is good practice for device protection during LTS. Dry packing has a finite effective life for moisture protection due to the limited absorption capability of the desi

37、ccant and moisture penetration through the packing material. 4.1.2 Desiccant Refer to J-STD-033. NOTE If a storage condition other than 38 C /90% RH is utilized, recalculation of the WVTR is recommended. The driving force for moisture to penetrate the bag is the water vapor pressure differential bet

38、ween inside and outside the bag. Consider the inside of the MBB at 0 mbar. The mbar outside the bag is dependent on temperature and humidity. The WVTR is a linear function of the water vapor pressure differential; therefore recalculate the effective WVTR. EXAMPLE: The water vapor pressure at 38 C/90

39、 % RH is 60 mbar; at 25 C / 80% RH, it is 25 mbar. If the WVTR is 0.002 g (100sqinch * day) at 38C /90% RH, it will be 0.002/60*25 = 0.0008 g (100sqinch*day) at storage condition 25 C / 80% RH. 4.1.3 Humidity Indicator Card (HIC) Refer to J-STD-033. Assurance should be made that there is no degradat

40、ion in HIC performance during LTS. 4.1.4 Dry Nitrogen Atmosphere Nitrogen environments of 5% RH or less shall be in accordance with MIL-PRF-27401, Type 1 Gas, Grade C (99.995%). The use of other atmospheric conditions should be evaluated to ensure performance to LTS requirements. JEDEC Publication N

41、o. 160 Page 5 4.1 Materials (contd) 4.1.5 High purity dry air Atmosphere Maximum 5% RH, 0.04% CO2, 0.001% Cl2, 0.001% S, 0.001% P. The use of other atmospheric conditions should be evaluated to ensure performance to LTS requirements. 4.1.6 Storage Containers Material used in contact with or in close

42、 proximity to the wafer, die, or device surface must preserve product integrity. The container should provide protection from contamination, abrasion, and outgassing. When ESD concerns are warranted, proper materials and procedures should be used. 4.1.7 Foams, Packing Material and Protective Cushion

43、ing If used, material for LTS should not contaminate contents. Nitrogen-filled, closed cell foam is an example of a suitable material for LTS. If using a carbon-filled variant of this type of foam, take care to ensure that the carbon is fixed in the material and cannot shed particles during LTS. The

44、 packing material should be able to meet the LTS life. In particular, any packing item that could give rise to chemical or particulate contamination by long-term degradation should be avoided. Paper used to separate product (e.g., Tyvek , etc.) should be contaminant free and meet application ESD req

45、uirements. Materials coated with films to reduce static charge (i.e., ESD-coated) should be evaluated for outgassing concerns. Barrier materials as defined by MIL-PRF-131 should be tested to confirm LTS performance is acceptable. 4.2 General Storage Environment The storage environment for LTS packag

46、ed products should be controlled to minimize vibrations and product handling. Temperature control is important to provide protection from material decomposition and warpage mechanisms. It is important to prevent rapid temperature changes that could cause moisture condensation based upon the saturate

47、d vapor pressure of water in the container or thermal shock failure mechanisms. Temperature ramp rates should be controlled so the product maintains a thermal equilibrium to prevent thermal shock or moisture condensation. Humidity control is important as MBB integrity is directly related to the humi

48、dity exposure. Maximum storage time depending upon HIC response can be calculated using the Water Vapor Transmission Rate (WVTR) as defined in J-STD-020. General warehouse temperature and humidity storage environments should be evaluated for wafer, die, and device LTS concerns. Typical warehouse tem

49、peratures are less than 40 C. Typical warehouse humidity is less than 90% RH. Consideration should be made with the storage materials to reduce the likelihood of outgassing. Outgassing can be related to temperature exposure of the LTS material (including foams, trays, gaskets, insulators, topical antistats, etc.), thus evaluation of maximum storage temperatures should be performed. Product exposed to the environment outside of LTS packaging should follow J-STD-033 for storage. Typical temperature ranges for wafers, dice, and modules not in LTS are 20