ImageVerifierCode 换一换
格式:PDF , 页数:30 ,大小:313.03KB ,
资源ID:806995      下载积分:10000 积分
快捷下载
登录下载
邮箱/手机:
温馨提示:
如需开发票,请勿充值!快捷下载时,用户名和密码都是您填写的邮箱或者手机号,方便查询和重复下载(系统自动生成)。
如填写123,账号就是123,密码也是123。
特别说明:
请自助下载,系统不会自动发送文件的哦; 如果您已付费,想二次下载,请登录后访问:我的下载记录
支付方式: 支付宝扫码支付 微信扫码支付   
注意:如需开发票,请勿充值!
验证码:   换一换

加入VIP,免费下载
 

温馨提示:由于个人手机设置不同,如果发现不能下载,请复制以下地址【http://www.mydoc123.com/d-806995.html】到电脑端继续下载(重复下载不扣费)。

已注册用户请登录:
账号:
密码:
验证码:   换一换
  忘记密码?
三方登录: 微信登录  

下载须知

1: 本站所有资源如无特殊说明,都需要本地电脑安装OFFICE2007和PDF阅读器。
2: 试题试卷类文档,如果标题没有明确说明有答案则都视为没有答案,请知晓。
3: 文件的所有权益归上传用户所有。
4. 未经权益所有人同意不得将文件中的内容挪作商业或盈利用途。
5. 本站仅提供交流平台,并不能对任何下载内容负责。
6. 下载文件中如有侵权或不适当内容,请与我们联系,我们立即纠正。
7. 本站不保证下载资源的准确性、安全性和完整性, 同时也不承担用户因使用这些下载资源对自己和他人造成任何形式的伤害或损失。

版权提示 | 免责声明

本文(JEDEC JEP167-2013 Characterization of Interfacial Adhesion in Semiconductor Packages.pdf)为本站会员(sumcourage256)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

JEDEC JEP167-2013 Characterization of Interfacial Adhesion in Semiconductor Packages.pdf

1、JEDEC PUBLICATION Characterization of Interfacial Adhesion in Semiconductor Packages JEP167 APRIL 2013 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subse

2、quently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in

3、 selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or art

4、icles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to prod

5、uct specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this stan

6、dard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative conta

7、ct information. Published by JEDEC Solid State Technology Association 2013 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charg

8、e for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th

9、Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Publication No. 167 -i- CHARACTERIZATION OF INTERFACIAL ADHESION IN SEMICONDUCTOR PACKAGES Contents Introduction ii 1 Scope 1 2 Terms and definitions . 1 3 References 2 4

10、Die adhesion . 2 4.1 Molded wire bond package 3 4. 2 Flip chip package 4 5 Characterization methods 6 5.1 Die shear test 6 5.2 Button shear test . 8 5.3 (Leadframe) pull test 9 5.4 Stud pull test 9 5.5 Laser spallation technique 10 5.6 Flip chip tensil pull test for bumps . 11 5.7 Peel test 12 5.8 W

11、edge test 13 5.9 Cantilever beam test . 14 5.10 Three-point bend test . 14 5.11 Mixed-mode bend test 15 6 Comparison and assessment of methods . 16 6.1 Scope and application range of the method . 16 6.1.1 Failure characterization techniques . 17 6.1.2 Methods for interface characterization . 18 6.1.

12、3 Methods for measurement of adhesion strength . 19 6.2 Failure mechanisms . 19 7 Summary and recommendations . 20 Annex A (informative) Flip chip package interfaces . 21 Annex B (informative) Molded leadframe-package interfaces 21 Annex C (informative) Bibliography 22 JEDEC Publication No. 167 -ii-

13、 Introduction Delamination of the interfaces between the die, lead frame and the ambient materials is one of the major issues of IC reliability. There are several methods described in the literature how to characterize the adhesion of the die at these interfaces. Some of them are standardized. This

14、publication gives guidance which method to choose for material selection, qualification or monitoring. JEDEC Publication No. 167 Page 1 CHARACTERIZATION OF INTERFACIAL ADHESION IN SEMICONDUCTOR PACKAGES (From JEDEC Board Ballot JCB-12-67, formulated under the cognizance of the JC-14.1 Subcommittee o

15、n Reliability Test Methods for Packaged Devices.) 1 Scope This document identifies methods used for the characterization of die adhesion. It gives guidance which method to apply in which phase of the product or technology life cycle. NOTE Inclusion in this directory of methods does not imply applica

16、bility to all die-package configurations. 2 Terms and definitions die adhesion: Steady or firm attachment between die and an adhesive material e.g. mold compound adhesion strength: the force needed to separate two materials by an defined method like shear or pull. creep: the tendency of a solid mate

17、rial to slowly and permanently deform under stress. Mode I (crack failure mode): An opening or tensile crack caused by loading normal to the crack Mode II (crack failure mode): A sliding or in-plane shear crack caused by loading parallel to the crack surface sliding direction. NOTE The crack surface

18、s slide over one another in direction perpendicular to the leading edge of the crack. Mode III (crack failure mode): A tearing or out-of-plane shear crack caused by loading coplanar to the crack surface and perpendicular to the crack propagation direction. wear: The erosion of material from a solid

19、surface caused by interaction with another material. JEDEC Publication No. 167 Page 2 3 References ASTM D3165, Standard Test Method for Strength Properties of Adhesives in Shear by Tension Loading of Single-Lap-Joint Laminated Assemblies ASTM D3433, Standard Test Method for Fracture Strength in Clea

20、vage of Adhesives in Bonded Metal Joints ASTM D3762, Standard Test Method for Adhesive-Bonded Surface Durability of Aluminum (Wedge Test) ASTM D903, Standard Test Method for Peel or Stripping Strength of Adhesive Bonds ASTM F459, Standard Test Methods for Measuring Pull Strength of Microelectronic W

21、ire Bonds JESD22-B109, Flip Chip Tensile Pull JESD22-B115, Solder Ball Pull MIL-STD-883 Meth 2012.7, Radiography MIL-STD-883 Meth 2019, Die Shear Strength MIL-STD-883 Meth 2027, Substrate Attach Strength MIL-STD-883 Meth 2030, Ultrasonic Inspection of Die Attach MIL STD 883 Meth 2031.1 SEMI G63-95,

22、Test Method for Measurement of Die Shear Strength SEMI G69-0996, Test Method for Measurement of Adhesive Strength between Leadframes and Molding Compounds 4 Die adhesion Failure mechanisms directly or indirectly affecting die adhesion are fatigue mechanisms, creep, wear, Interfacial fracture, and no

23、nwetting due to contamination or residues. The effect on time to failure depends very much on design and construction of the package. JEDEC Publication No. 167 Page 3 4.1 Molded wire bond package There are two major techniques for attaching a die to a die pad, adhesive or solder. For adhesives polyi

24、mide, epoxy or silver filled glass is used. A sketch of the three critical interfaces of this type of package is shown in Figure 1. diedie padfilletbond linemould compoundABCA) die adhesive pad, B) die mold compound, C) mold compound die pad/leadframe Figure 1 Die adhesion interface Delamination at

25、C does not directly affect a die-related interface, but it should be taken into account because of its influence on delamination and related failure modes at die-related interfaces. The attach process with adhesives has two potential failure causes: o excessive die attach fillet resulting in die att

26、ach contamination and problems when performing die shear tests; o too little die attach fillet resulting in die delamination or die cracking. The eutectic process typically uses alloys Sn-Ag, Sn-Ag-Cu, Au-Si, Au-Sn, Pb-Sn or Au. Here voiding especially large voids are the main risk. These voids chan

27、ge the stress situation and therefore are the cause of die cracking. Table 1 gives an overview of the cause-failure correlation at die interfaces. Delamination failures are covered by the column “die lifting”. JEDEC Publication No. 167 Page 4 4.1 Molded wire bond package (contd) Table 1 Cause failur

28、e correlation, examples Failure Cause Die to mold separationDie Lifting from LF Die Cracking Adhesive Shorting Bond Lifting contamination X X excessive die attach voids X X incomplete die attach coverage X X inadequate die attach curing X X die overhang X insufficient bond line thickness X excessive

29、 die ejection force X absence of voids X incorrect die attach material viscosity X incorrect adhesive dispensation X Out gassing from D/A cure X X resin bleeding of the die attach material into the bond pads X 4.2 Flip chip package Flip chip packages have many interfaces which could delaminate or br

30、eak (see Figure 2. Cohesive failure modes are not covered in this publication. Stress related failures due to thermal load have been studied for the interfaces bump underfill 6 die mold compound 7 die underfill 7. Interface underfill-solder mask is not discussed here. Especially the adhesion of the

31、underfill is the most important factor affecting reliability of flip chip assemblies. An example of a detailed reliability analysis of a flip-chip-package can be found at reference 8. JEDEC Publication No. 167 Page 5 4.2 Flip chip package (contd) diePCBfilletunderfillmould compoundAsolderBCDAdhesion

32、A: Die MCB: Die UnderfillC: Bump UnderfillD: Underfill Solder maskFigure 2 Interfaces of flip-chip-packages (example) Depending on the design different geometrical or material properties have influence on the strength of degradation: PCB thickness, CTE and Youngs Modulus; underfill / adhesive CTE an

33、d Youngs Modulus; die size; surface treatment; wetting angle; fillet width and height; flux residues. Design specific sensitivity analysis should be done for stress intensity effect, energy release rate G and phase angle . JEDEC PuPage 6 5 CThis sectdie to its 5.1 DDie shearof determsubstratethe die

34、 tobetween:1) the di2) the diA typical1) a mec50 g, 2) a die the fo3) provi4) provitool s5) a binothe obblication Noharacterizaion gives ansurroundingie shear testesting as dining the st(such as thea stress thae-die attache attach madie shear tehanism thatwhichever tcontact toolrce uniformsions to e

35、nsusions to ensuo that the dicular microservation o. 167 tion methooverview omaterials. St escribed in rength of addie pad of ats parallel tomaterial intterial-substrster (Figureapplies the olerance is gthat makes ly from onere that the dre that the fe edge and cscope (10 tif the die andds n existin

36、g mtandard refMIL-STD-8hesion of a slead framethe plane oerface; and ate interface3) consists correct loadreater, the actual coend of the eie contact tixture holdiontact tool mes minimucontact tooFigure 3ethods usederences are g83, Methodemiconductor the cavitf die attach . of to the die wntact with

37、 tdge to the oool is perpenng the die mmay alwaysm magnificl while the t Die sheafor charactgiven. 2019 and Sor die to they of a hermesubstrate, reith an accurhe full lengtther, ndicular to tay be rotatebe aligned iation) and lest is being r test terizing the iEMI G63-9packages dtic packagesulting i

38、n aracy of 5%h of the die he die attachd with respin parallel toighting systeperformed. nterfaces of 5 is the procie attach ), by subjeca shearing strof full scaledge to appplane; ect to the coeach other,m to facilitathe ess ting ess e or ly ntact and te JEDEC Publication No. 167 Page 7 5.1 Die shea

39、r test (contd) For the die shear test done before molding, there is only preparation effort needed in cases where there is not enough space available for the contact tool. In these cases, the result can be affected by the preparation technique used. The force applied to the die during die shear test

40、ing must be sufficient to shear the die from its mounting or twice the lower specification limit for the die shear strength, whichever occurs first. The direction of the applied force must be perpendicular to the die edge and parallel to the die attach or substrate plane. After the initial contact h

41、as been made and the application of force starts, the relative position of the tool must not change vertically, i.e., it must be prevented from contacting either the die attach material or the substrate. A failure criterion for die shear strength is given as a function of area. The mode of separatio

42、n must also be classified into the following: 1) shearing of the die itself with silicon remaining; 2) separation of the die from the die attach material; 3) separation of both the die and die attach material from the package substrate. This method is most efficient if used for monitoring as long as

43、 data from a specific package are compared. Due to the influence of the fillet height, it is hard to compare adhesion data for different materials. For qualification it is an indicator test selecting parts with worse adhesion. There is no model available to correlate failure curves to operational fi

44、eld conditions Solder reflow temperatures induce high stress at the die and leadframe interface and at the same time the adhesion strength of most organic adhesive materials drop drastically at high temperature. Because of this combination, a large number of delamination failures occur during solder

45、 reflow. Thus it is useful to check die shear strength at high temperature. High-temperature die shear testing is also useful to test larger die whose die attach strength could easily exceed the tool capability. A high-temperature die shear test may be performed using the same tool as described abov

46、e together with a heated stage; the setup and test method is similar as for room temperature except for the stage temperature. Temperatures can be defined by the user. (Typical temperature is 240 C). The type of failure mode offers further insight into selection of materials. JEDEC PuPage 8 5.2 BThe

47、 buttodevice thenvironmbetween The test mapplicatiocalibratedSpecific processesThe measFinite eleenergy dedefined ithe methoblication Noutton shearn shear testat is assumeental effectmold compoethod is dens are desc, can be usestructures ha. Pull or benured adhesiment modelnsity, G ann the G-pd is t

48、ypical. 167 test (Figure 4) id to contains of moisturund and leascribed as oribed in the d. ve to be preding methove strength ing is used td . Dependlot. There isly used for ms used to qusome inhere and tempedframe or flFigure 4 ne out of thliterature 8pared, whicd can be useis calculatedo obtain in

49、ting on the sno absoluteaterial seleantify the inent cracks 5rature and isip chip packButton sheree alternati. Standard sh makes it id as an altein N/mm ferfacial streshearing heiggating critection. terfacial stre,8. It also ctypically uages. ar test ve ones in Shear test eqndependent ernative test prom the peasses and to cht a theoretrion for quangth of twoovers the insed for the iEMI G69-0uipment, whfrom costly rocedure. k load. alculate inteical failure clification pulayers withfluenc

copyright@ 2008-2019 麦多课文库(www.mydoc123.com)网站版权所有
备案/许可证编号:苏ICP备17064731号-1