JEDEC JEP176-2018 ADAPTER TEST BOARD RELIABILITY TEST GUIDELINES.pdf

1、 JEDEC PUBLICATION ADAPTER TEST BOARD RELIABILITY TEST GUIDELINES JEP176 JANUARY 2018 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed

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4、 or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification

5、 and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made

6、unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative contact information. P

7、ublished by JEDEC Solid State Technology Association 2018 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell t

8、he resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240

9、South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Publication No. 176 -i- ADAPTER TEST BOARD RELIABILITY TEST GUIDELINES FOR INTEGRATED CIRCUITS CONTENTS Introduction 1 1 Scope 2 2 Terms and definitions 2 3 Reference documents 3 4 General

10、 requirements 5 4.1 Objective 5 4.2 Stress/test parameters 5 4.3 Electrical Test 5 5 Adapter test board design 5 6 Recommended reliability tests 7 6.1 General tests 7 6.2 Mounting IC components on adapter test boards & preconditioning recommendations 7 6.3 Temperature cycling (TC) recommendations 8

11、6.4 Highly accelerated stress test recommendations 9 6.5 High temperature storage life recommendations 9 6.6 High temperature operation life recommendations 6.7 Non-volatile memory endurance cycling and data retention recommendations 9 9 6.8 Failure analysis recommendations 10 Annex A (informative)

12、Examples of adapter test board designs 11 Annex B (informative) Optical inspection criteria 15 JEDEC Publication No. 176 -ii- Introduction Traditionally, integrated circuits packaged in through-hole packages and surface mount packages can be placed directly into Automatic Test Equipment (ATE) for el

13、ectrical test for reliability tests and production. However, for solder-bump-based packages, this test method becomes challenging. One alternative method of performing electrical tests and reliability tests is to mount integrated circuits in solder bump-based-packages onto adapter test boards, which

14、 enables the connection between the integrated circuit devices to the biased reliability boards and ATE. Chip-Scale Packages (CSP), Flip-Chip Die that are to be assembled directly to boards, and other Fine-Pitch Packages (FPP) may benefit from use of an electrical test adapter board for component-le

15、vel reliability testing. This document provides guidelines on testing of integrated circuit devices mounted on adapter test boards specifically for the purpose of performing reliability tests to identify component-level failure mechanisms. The use of adapter test boards is a lower cost alternative t

16、o using custom sockets on the biased reliability boards and ATE interface boards. This publication recommends that JESD47 or another JEDEC qualification standard be used. This document augments those requirements with guidance on some testing that may be preferable to execute in a format where the s

17、upplied device is mounted on an adapter test board either for the purpose of handling efficiency through the reliability stress or electrical test evaluations. The reliability stress test is performed to assess the robustness of the chip-scale, flip-chip, and fine-pitch package manufacturing process

18、 and/or to determine whether there are chip-package interaction effects. These considerations apply to devices in chip-scale packaging, flip-chip direct attach, and fine-pitch packages. This document also offers guidelines for mitigating the risk of adapter test-board-related failure mechanisms. JED

19、EC Publication No. 176 Page 1 ADAPTER TEST BOARD RELIABILITY TEST GUIDELINES (From JEDEC Board Ballot JCB-17-36, formulated under the cognizance of the JC-14.3 Subcommittee on Silicon Devices Reliability Qualification and Monitoring.) 1 Scope This publication describes guidelines for applying JEDEC

20、reliability tests and recommended testing procedures to integrated circuits that require adapter test boards for electrical and reliability testing. These tests are used frequently in qualifying integrated circuits as a new product, a product family, or as products in a process which is being change

21、d. Integrated circuit devices in various packages that cannot be tested directly with the Automated Test Equipment (ATE) are each mounted on an adapter test board for testing. Some common devices mounted on adapter test boards for test purposes are Chip-Scale Package, Flip-Chip Die, and Fine-Pitch P

22、ackage devices (e.g., 64-Lead QFN package with 0.50-mil lead pitch). This document provides guidelines for adapter test board-level reliability tests, recommended testing procedures, test board designs, and construction materials. It is aimed to provide a reproducible assessment of the reliability p

23、erformance of integrated circuit devices while duplicating the failure modes normally observed during product life cycle. The reliability test recommendations do not apply to the following: a) Integrated circuits that are stressed and/or tested in an electrical socket. b) WLCSP devices that are stre

24、ssed and/or tested using a wafer-level probe card. c) Second-level solder joint reliability tests such as drop test, thermal cycle test, bend test, etc. These reliability tests are capable of evaluating and simulating package and device failures in an accelerated manner compared to use conditions. T

25、he guidelines prescribed in this publication are not aimed for reliability tests for devices in extreme use conditions such as military applications, automotive under-the-hood applications, or uncontrolled avionics environments. Each reliability test should be examined for: a) Any potential new and

26、unique failure mechanisms, b) Any situation where these tests and/or conditions may induce false failures. JEDEC Publication No. 176 Page 2 2 Terms and definitions adapter test board: A printed circuit board constructed specifically for the purpose of mounting integrated circuits for stress and reli

27、ability testing purposes. NOTE An adapter test board enables the electrical connection between the test equipment and the integrated circuit (IC). chip-scale package (CSP): A package whose area is generally no greater than 120% of the area of the semiconductor device it contains. component: A consti

28、tuent part. failure: The loss of the ability of a device or component to meet the electrical or physical performance specifications that it was intended to meet. flip-chip die: An unpackaged die whose interconnection to a substrate is formed through solder joints. integrated circuit (IC): A circuit

29、in which all or some of the circuit elements are inseparably associated and electrically interconnected so that it is considered to be indivisible for the purposes of construction and commerce. packaged device: A semiconductor device within an enclosure that allows electrical connections to, and pro

30、vides mechanical and environmental protection for, that device. redistribution metallization layer (RDL): Often called “runners or “traces” that allow re-routing the signal path from the die peripheral input/output (I/O) to an area array of new bump locations, often with significant loosening of eff

31、ective bump pitches. sample: A set of individuals taken from a population. second-level assembly: The attachment of a component to the next level of assembly packaging. JEDEC Publication No. 176 Page 3 3 Reference documents JESD22-A102, Accelerated Moisture Resistance Unbiased Autoclave JESD22-A103,

32、 High Temperature Storage Life JESD22-A104, Temperature Cycling JESD22-A113, Preconditioning of Nonhermetic Surface mount Devices Prior to Reliability Testing JESD22-A110, Highly Accelerated Temperature and Humidity Stress Test (HAST) JESD22-B117, Solder Ball Shear JESD47, Stress-Test-Driven Qualifi

33、cation of Integrated Circuits J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices J-STD-012, Implementation of Flip Chip and Chip Scale Technology IPC-9701, Performance Test Methods and Qualification Requirements for Surface mount Solder Attachment

34、s JESD22-B111, Board Level Drop Test Method of Components for Handheld Electronic Products JEP154, Guideline for Characterizing Solder Bump Electromigration under Constant Current and Temperature Stress JESD22-A105, Power and Temperature Cycling Telcordia GR-78-CORE, Generic Requirements for the Phy

35、sical Design and Manufacture of Telecommunications Products and Equipment, Section 13.1.1 and 13.1.2 IPC-TM-650, Test Methods Manual Method 2.6.3.3 Surface Insulation Resistance, Fluxes IPC-TM-650, Test Methods Manual Method 2.6.3.7 Surface Insulation Resistance IPC-5702, Guidelines for OEMs in Dete

36、rmining Acceptable Levels of Cleanliness of Unpopulated Printed Boards JEDEC Publication No. 176 Page 4 4 General requirements 4.1 Objective An adapter test board is defined as a Printed Circuit Board (PCB) assembly constructed specifically for the purpose of component-level reliability testing. For

37、 adapter test board design considerations and material guidelines, see Section 5 of this document. Examples of several variations of adapter test board designs are provided in annex A of this document. Other variations of adapter test boards not provided in Annex A can also be used for the reliabili

38、ty tests described in this document provided that the PCB configurations do not in any way hinder the testing or stressing of the integrated circuit device. 4.2 Stress/test parameters Procedures should be consistent with the requirements of JESD47. This includes, but is not limited to: lot and produ

39、ction recommendations, re-usability of test samples, and definition of electrical test failure after reliability stress. 4.3 Electrical test Electrical test equipment with capabilities to perform appropriate testing on devices should be used to test electrical parameters (e.g., data sheet values, in

40、-house specifications, etc.). This may require the use of special electrical test boards and sockets. The electrical tests performed for integrated circuit devices mounted on an adapter test board should be consistent with ones performed for those IC devices at the component level. JEDEC Publication

41、 No. 176 Page 5 5 Adapter test board design The following design and construction guidelines are recommended for adapter test board reliability tests: 1. Clearances Adapter test board should allow sufficient space between the IC component and the edge of the adapter test board to simulate the field

42、condition during its product life cycle and to allow for easy handling. A minimum gap of 5 mm is recommended between the IC component and edge of the adapter test board. Adapter test boards with through-hole connectors should be designed to minimize the possibility of contamination of the IC compone

43、nts during the soldering process. A minimum gap size of 3.8 mm between the IC component and the nearest through-hole is required. For both edge connector and through-hole connectors, larger spacing is preferred since it can help alleviate the chance of inadvertent flux contamination. 2. Layout Adapt

44、er test boards should be panelized when possible to improve the manufacturability. Panel size should be minimized in order to help ensure highly accurate solder mask registration. Smaller panel size also decreases the risk of warpage during manufacturing. 3. Thickness Due to second-level solder join

45、t stresses on the device while mounted to an adapter test board during reliability testing, overall board thickness should be carefully considered. Lowering the board thickness will result in a lower overall solder joint stress level. Thinner boards can also result in more warpage, however, resultin

46、g in manufacturing difficulties. It is recommended that the thinnest board possible be used that allows for good manufacturing. Customer board thickness should also be taken into account, and adapter test board thickness should match the end application as closely as possible if known. A typical ada

47、pter test board nominal thickness is 0.75-1.5 mm. Please note that the board thickness maybe fixed based on the mating connectors/sockets in all cases with the exception of through-hole type of adapter boards. 4. Layers There is no requirement for number of layers in the adapter test board design, a

48、lthough some typical guidelines can be followed. The lowest cost option will be a 1-2 layer design, and is most likely suitable in most situations (especially lower pin count packages). The copper distribution should be as symmetrical as possible in all axes to minimize warpage. Two layer boards are

49、 preferred since one layer boards w/asymmetric metal traces are more prone to warpage. The preference is to have a two layer board with metal traces, which are balanced at the top and bottom of the board. 5. Vias The usage of vias should be minimized when possible. If vias are employed to establish connections, larger vias are preferred for better manufacturability during the plating process. If via-in-pad connections are necessary, it is recommended that the vias be filled and planarized. For space reasons uVias may need to be considered which should be filled for smaller