JEDEC JEP179-2006 Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface- Mount Components《组装的固态表面贴装元件的测试驱使鉴定和故障机理分析》.pdf

1、JEDEC PUBLICATION DDR2 SPD Interpretation of Temperature Range and (Self-) Refresh Operation JEP179 JUNE 2006 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level an

2、d subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purch

3、aser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents

4、 or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach

5、to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with th

6、is standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Published by JEDEC Solid State

7、 Technology Association 2006 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Please refer to

8、the current Catalog of JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain p

9、ermission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Publication No. 179 -i- DDR2 SPD INTERPRETATION OF TEMPERA

10、TURE RANGE AND (SELF-) REFRESH OPERATION Introduction The JEDEC standard DDR2 SDRAM must satisfy the requirement of 85C tCASE(max) operation at all times (Byte 47, bits 4:7 = 0000). There is an optional, higher tCASE operation allowed, up to 95C (Byte 47, bits 4:7 = 1010). If the optional higher tCA

11、SE limit is supported, there are two options that may or may not be supported to enhance the higher tCASE limit. These two options are vendor determined: (1) Double refresh required, (2) High Temp SR supported. If the base DRAM, i.e. tCASE(max) of 85C is specified, the two optional features are not

12、required (but must be set to a default zero value.) If, on the other hand, the optional tCASE(max) of 95C is supported, then the other two options must be specified as determined by the particular SDRAM supplier being used. JEDEC specifies that if a tCASE of 95C is used, then the refresh to the DRAM

13、 must be doubled (Byte 49, bit 1 = 1); however, a DRAM vendor may allow the normal refresh rate to be used (Byte 49, bit 1 = 0). Also, a particular SDRAM may support the higher tCASE option during self refresh (Byte 49, bit 0 = 1) while other SDRAMs will not (Byte 49, bit 0 = 0). JEDEC Publication N

14、o. 179 -ii- JEDEC Publication No. 179 Page 1 DDR2 SPD INTERPRETATION OF TEMPERATURE RANGE AND (SELF-) REFRESH OPERATION (From JEDEC Board Ballot, JCB-05-117, formulated under the cognizance of the JC-42.3 Subcommittee on RAM Memories.) 1 Scope The purpose of this document is to explain the meaning o

15、f SPD setting (JESD21 SPD section) for DDR2 SDRAM (JESD79-2) in normal and extended temperature operationy67. 2 DRAM Type tREFI = 7.8 us below 85 C tREFI = 7.8 us below 85 C & tREFI = 3.9 us above 85 C. Program EMRS(2)A7 properly to 0 or 1 depending on the Self-Refresh Entry temp. If SR mode is ente

16、red above 85 C, wake up the DRAM once temp drops below 85 C, re-program the EMRS(2)A7 to 0, then put it into Self-Refresh mode again. Options for simpler control. Use fixed tREFI = 3.9 us for the full temperature range of 0 C to 95 C. or Set EMRS(2)A7 to 1 and never update it. or Dont perform the wa

17、ke up sequence even if the temperature drops below 85 C. Rev. 9/02 Standard Improvement Form JEDEC JEP179 The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard. Individuals or companies are invited to submit comm

18、ents to JEDEC. All comments will be collected and dispersed to the appropriate committee(s). If you can provide input, please complete this form and return to: JEDEC Attn: Publications Department 2500 Wilson Blvd. Suite 220 Arlington, VA 22201-3834 Fax: 703.907.7583 1. I recommend changes to the fol

19、lowing: Requirement, clause number Test method number Clause number The referenced clause number has proven to be: Unclear Too Rigid In Error Other 2. Recommendations for correction: 3. Other suggestions for document improvement: Submitted by Name: Phone: Company: E-mail: Address: City/State/Zip: Date: