JEDEC JEP65-1967 Verification of Maximum Ratings of Power Transistors Test Procedures for《功率晶体管最大等级认证的测试程序》.pdf

1、- EIA JEP65 67 m 3234600 0003349 2 m /-7 DECEMBER 1967 TEST PROCEDURES FOR VERIFICATION OF MAXIMUM RATINGS OF POWER TRANSISTORS PRICE $2.00 FORMULATED BY JEDEC SEMICONDUCTOR DEVICE COUNCIL . JEDEC PUBLICATION NO. 65 - .- .- -_ Q= k L* EIA JEPb5 67 m 323L1600 0003350 7 m Published by ELECTRONIC tNDUS

2、TRIES ASSOCIATION Engineering Department 2001 Eye Street, N. W., Washington, D. CI 20006 EIA JEPbS 67 3234600 0003353 O m JEDEC PUBLICATION NO. 65 TEST PROCEDURES FOR VERIFICATION OF MAXIMM RATINGS OF POWER TRANSISTORS DECEMBER i967 FOREWORD This publication describes tests which are intended to rep

3、resent only the verification of maximum ratings; they are not tests for performance or quality level. that this material be used in conjunction with formats devel- oped for device registration and defining data. It is proposed All values specified are nominal and should be maintained The procedures

4、in this document were prepared by the JS-6 within equipment capabilities and good engineering practice. Committee on Power Transistors and approved for publication by the JEDEC Semiconductor Device Council. - EIA JEPb5 67 W 3234b00 0003352 2 W I L JS-6 - T1-1 Minimum Storage Temperature, Maximum Rat

5、ings Tst min. 1. General The minimum storage temperature shall be based on the capability of any individual transistor to meet the test described below. 2. 3. 4. Test Conditions a. T as specified. stg b. Duration of the test- to be one cycle, 6 hours at minimum specified storage temperature Pro ce d

6、ure a Adjust the temperature in a temperature-controlled enclosure to the specified storage temperature. b. Place test transistors in the enclosure. C. The order of the procedure may be reversed. Evaluation a. T-he device shall be allowed t.o reach thermal O equilibrium at 25 C prior to the evaluati

7、on measurements. b. The device shall still be capable of meeting all the Electrical Characteristics of the Registration. P- . -1- EIA JEPb5 b7 W 3234600 0003353 4 W 1 . JS-6,- T1.2 Maximum Storage Temperature, Maximum Ratings, Tst 1, General The maximum storage temperature shall be based on the capa

8、bility of any individual transistor to meet the test described below. 2. Test Conditions a T as specified. stg b. Duration of the test to be one cycle, six hours at the maximum specified storage temperature. 3. Procedure a. Adjust the temperature in a temperature-controlled enclosure to the specifie

9、d storage temperature. b. Place test transistors in the enclosure. C. The order of the procedure may be reversed. 4. Evaluation a. The device shall be allowed to reach thermal equilibrium at 25OC prior to the evaluation measurements . b. The device shall still be capable of meeting all the Electrica

10、l Characteristics of the Registration. . -2- .- ; . ! my be infinite. The characteristics b. The transistor case temperature must be + 25OC. C. The collector current at the maximum rating of VCE must be as specified. If this is a sustaining test, this current should be high enough to insure that the

11、 transistor is in the sustaining region where the collector voltage is relatively insensitive to collector current over a large range of currents. d. Duration of the test shall be that time adequate to make the reading. e. The pulse repetition rate should be specified. EIA JEPb5 b7 m 3234600 0003358

12、 3 m t-. A PulsedBia fb Vert . Def . V iI RS a. be from llO1t to infinity, All circuit values must be specified; RiB may may be ltOf*. BB . b. The transistor case .temperature must be +25OC. C. The collector current at the.maximum rating of VCE must be as specified. If this is a sustaining test, thi

13、s current should be high enough ,to ensure that the transistor is in the susta.ining region where the collector voltage is relatively insensi- tive.to collector current over a large range of current s. d. to make the reading, a Duration of the test shall be that time adequate e. The pulse repetition

14、 rate and duty cycle should be specified. 3. Procedure 3.1 Inductive Method (T 5.1) a. Adjust the bias supplies to the specified test conditions. .b, Decrease R until the intersection of the specified collector current and V rating is reached. See following illustration. L CE : EIA JEPb5 67 M 323460

15、0 0003359 5 M I I as spe c- I cified - 11 Oscilloscope Dis pl ay IV rating ce Os ci lloscope C. Suitable precautions should be taken against transient spikes and oscillations. 3.2 Pulsed Collector Method (T 5.2) a. b. is obtained. Adjust VBB to the specified value. Increase Vcc unfil the specified c

16、ollector current 4. Evaluation (T 5.1 and T 5.2) a. The device shall be allowed to reach thermal equilibrium at + 25 C prior to the evaluation measurements. b. The device shall still be capable of meeting all the Electrical Characteristics specified in the Registration, O EIA JEP65 67 W 3234600 0003

17、360 II W L DC Current Source _i JS-6 - T6 Continuous.Col1ector Current, Maximum Rating DC Current Source - A 1. General The maximum continuous collector current rating shall be based on the capability o any individual transistor to operating in the test circuit illustrated below: 2. Test Circuit and

18、 CorPditions (Polarity of transistor - . C. Duration of the test to be five minutes, 3. Procedure a. Increase the base drive to obtain the specified base current, IB. b. Increase the collector drive to obtain the rated collector current, IC 4. Evaluation a. The device shall be allowed to reach therm

19、al equilibrium at 25OC prior to the evaluation measurements. b, .The device shall stll be capable of meeting all the Electrical Characteristics specified in the Regist- ration. -9- EIA JEP65 67 3234600 0003363 3 = 1 JS-6 - T7 Pulsed Collector Current, Maximum Rating 1. General The maximum pulsed col

20、lector current rating shal.1 be based on the capability of any individual transistor to operate in the test circuit illustrated below. 2. Test Circuit and Conditions (Polarity of transistor - PNP, NPN, must be observed.) Oscilloscope IMO RS + i _ri- RBB I vcc Pulse - - BB Generator - A - - a. The tr

21、anslator case temperature must be +25 C. b. The amplitude, wave-shape (rise time, fall time, and puise width), and duty cycle of the base drive pulse shall be specified. and must .be specified. BB %B d. reading Duration of the test shaU be that time adequate to make the 3. Procedure a. Adjust the pu

22、lse generator to obtain the specified drive pulse. b . Aajust Vcc to obtain the rated pulsed collector current, ICMe 4. Evaluation a. The device shall be allowed to reach thermal equil- ibrium at 25 C prior to the evaluation measurement. b. The device shall still be capable of meeting all the Electr

23、ical Characteristics specified in the Regist- ration. O a -_ . Current Source I. EIA JEPb5 67 I 3234600 O003362 5 m JS-6 - “8 Continuous Base Current, Maximum Rating - a 1. General The.maximum continuous base current rating shall be based on the capability of any individual transistor to oper- ate i

24、n the test circuit illustreted below. 2. Test Circuit and Conditions (Polarity of transistor - PNP, NPN, - must be-observed) e T a. sbell be specified. The transistor owe temperature which must not be exceded b. Duration of the test to be five minutes. 3. Procedure Adjust the-current source to obtai

25、n the rated base current, IBO 4. Evaluation The device shall be allowed to reach thermal a. equilibrium at 25 O C prior to the evaluation measurements. b. Electrical Characteristics specified in the Registration. The device shall still be capable of meeting all the Y -11- EIA JEPbS b7 W 3234b00 0003

26、363 7 W JS-6 - T9 Pulsed Base Current, Maximum Ratin RS must be non-inductive and small sucs that RS vcc VBB - 20 IC and RBB are selected to enhance switching by cutting off transistor when pulse is in “off“ condition. and IEBO limits must be observed. BV b. The transistor case temperatureemust be s

27、pecified. C. rise and fall times must be specified. d. lead Inductance and power suppu characteristics Pulse width and duty cycle must be stated. Rtlse generator Good engineering practice must be used to eliminate effects of EIA JEPb5 b7 M 3234b00 0003373 b M L Forward Bias, Maximum Operating Condit

28、ions (continued) 3. Procedure a. Adjust the bias supplies to the specified test condition, b. Increase the pulse amplitude of the pulse generator to ,obtain the specified collector current,as defined by the voltage, current, and time relationship of the point to be verified. 4. Evaluation a. The device shall be allowed to reach thermal equilibrium at + 25 C prior to the evaluation measurements. O _. b. The device shall still be capable.of meeting all the Electrical Characteristics specified in the Registration. -20- .