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本文(JEDEC JESD1-1982 Leadless Chip Carrier Pinouts Standardized for Linear-s《无引线芯片座引脚分配的线性标准化》.pdf)为本站会员(李朗)主动上传,麦多课文库仅提供信息存储空间,仅对用户上传内容的表现方式做保护处理,对上载内容本身不做任何修改或编辑。 若此文所含内容侵犯了您的版权或隐私,请立即通知麦多课文库(发送邮件至master@mydoc123.com或直接QQ联系客服),我们立即给予删除!

JEDEC JESD1-1982 Leadless Chip Carrier Pinouts Standardized for Linear-s《无引线芯片座引脚分配的线性标准化》.pdf

1、- EIA JESDL 82 m 3234b00 OOOLi562 7 m / . -4 * C c c EIA JESDL A2 3234600 0004563 9 - n NOTICE This JEDEC Standard contains material which has been prepared and progres- sively reviewed and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. (-

2、 JEDEC Standards are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating inter- changeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his p

3、articular need. Existence of such standards shall not in any respect preclude any member or non-member of JEDEC from manufacturing or selling products not conforming to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members whether the

4、standard is to be used either domestically or internationally. JEDEC Standards and Publications are adopted by JEDEC without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor d

5、oes it assume any .obligation whatever to parties adopting the JEDEC Standards or Publications. -. = The information included in JEDEC Standards represents a sound approach to produot specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEk orga

6、nization there are procedures whereby a JEDEC Standard may be further processed and ultimately become an EIA Standard. Inquiries, comments, and suggestions relative to the content of this JEDEC Standard should be addressed to the JEDEC Executive Secretary at the EIA Headquarters. L JEDEC c. Electron

7、ic Industries Association . . 2001 Eye Street N.W. Washington, D.C. . 20006 . .I. - ELECTRONIC INDUCTRC ACOCIATION- . Y Engineering Department 2001 Eye Street, N.W. Washington, D.C. -20006 . . PRICE: $5.00 ., Printed in 1J.S.A, c -. EIA JESDL 82 m 3234600 0004564 O m 3 JE.DEC STANDARD No. 1 LEADLESS

8、 CHIP CARRIER PINOUTS STANDARDIZED FOR LINEARS This JEDEC Standard was formulated under the cognizance of the JEDEC JC.41 Committee on Linear Integrated Devices. NOTE: Numbering of JEDEC Standards follows a numerical sequence which does not necessarily relate to the publication date of the document.

9、 ,r EIA JESDL 82 3234600 00045b5 2 M =. + JEDEC Standard No. 1 Page 1 LEADLESS CHIP CARRIER PINOUTS STANDARDIZED FOR LINEARS The following criteria shall be used to convert existing DIP pin-outs for op-amps, comparators, and D/A converters, to chip carrier packages: A. 8. C. D. Chip Carrier Packages

10、 to be used shall be either the: (1) (2) Device Conversion shall be as follows! 20-lead, .350“ x .350“, Type C package, or the 28-lead, .450“ x .450“,.Type C package DIP PACKAGE CHIP CARRIER PACKAGE 8 - LEAD 14 - LEAD 16 - LEAD 18 - LEAD 20 - LEAD 20 - LEAD 24 - LEAD 28 - LEAD 28 - LEAD The pin-out

11、conversions shall be in accordance with the diagram shown in Figures 1 through 6. package/pinout. Each device shall be pinned out based on its present Thus a part now in a 8 lead package shall be pinned out in accordance with the 8 lead conversion to 20 lead chip carrier. able in more than one pinou

12、t then its lowest pin count package will be used to define the conversion to chip carrier pinouts. this rule is 10 lead parts. They are also always available in 14 lead versions and will therefore use the 14 lead conversion. If a part is presently avail- The single exception to The “optional“ versio

13、n of the 16 lead conversion is to be used only when the “preferred“ version will not work. . Its use is discouraged. Devices presently in 20 and 28 lead packages shall be pinned out 1:l in lead- less chip carriers. EIA JESDL 82 W 3234600 O004566 4 W . JEDEC Standard No. 3 Page.7 I 8 - LEAD PIN-OUT F

14、OR 20 - LEAD CHIP CARRIER (Top View) FIGURE 1 EIA JESDL 82 3234600 0004567 6 JEDEC Standard No. 1 Page 3 I4 - LEAD PIN-OUT FOR 20 - LEAD CHIP CARRIER (Top View) FIGURE 2 EIA JESDL 82 m 3234600 0004568 8 m JEDEC Standard No, 1 Page 4 16 - LEAD PIN-OUT FOR 20 - LEAD CHIP CARRIER (PREFERRED VERSION) (T

15、op View) U . FIG.URE 3 t EIA JESDL 82 W 3234600 0004569 T W JEDEC Standard No. 1 Page 5 16 - LEAD PIN-OUT FOR 20 - LEAD CHIP CARRIER (OPTIONAL VERSION) FIGURE 4 EIA JESDL 82 = 3234600 0004570 b JEDEC Standard No. 1 Page6 FOR 20 - LEAD CHIP CARRIER (Top View) FIGURE 5 . EIA JESDL 82 m 3234600 0004573 8 m .) . JEDEC Standard No. 1 Page 7 24 - LEAD PIN4W FOR 28 - LEAD CHIP CARRIER (Top View) FIGURE 6

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