1、JEDEC STANDARD Terms, Definitions, and Letter Symbols for Microcomputers, Microprocessors, and Memory Integrated Circuits JESD100B.01 (Minor Revision of JESD100-B, December 1999) DECEMBER 2002 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has
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3、acilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publicati
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5、formation included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further proce
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7、e address below, or call (703) 907-7559 or www.jedec.org Published by JEDEC Solid State Technology Association 2002 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the indivi
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10、Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 100B.01 -i- TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR MICROCOMPUTERS, MICROPROCESSORS, AND MEMORY INTEGRATED CIRCUITS CONTENTS PageForeword iii1 General terms and definitions 12 Time interval terms, definition
11、s, and letter symbols 152.1 Letter symbols 152.1.1 General form 152.1.2 Abbreviated forms 162.1.2.1 Unclassified time intervals 162.1.2.2 Classified time intervals 162.1.3 Subscripts 162.1.3.1 Subscript A - Type of dynamic parameter 172.1.3.1.1 Timing requirements 172.1.3.1.2 Characteristics 182.1.3
12、.2 Subscripts B and D - Signal name 192.1.3.3 Subscripts C and E - Transition of signal 202.1.3.4 Subscript F - Additional qualification 212.2 Definitions of classified time intervals 222.3 Examples of time interval symbols 252.3.1 Access times 262.3.2 Cycle times 272.3.3 Delay times 292.3.4 Disable
13、 times 312.3.5 Enable times 322.3.6 Fall times 332.3.7 Hold times 342.3.8 Propagation (delay) times 342.3.9 Pulse durations 342.3.10 Recovery times 352.3.11 Refresh time intervals 352.3.12 Rise times 352.3.13 Setup times 362.3.14 Transition times; rise and fall times 362.3.15 Valid times 36JEDEC Sta
14、ndard No. 100B.01 -ii- TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR MICROCOMPUTERS, MICROPROCESSORS, AND MEMORY INTEGRATED CIRCUITS CONTENTS (continued) Page2.4 Special letter symbols for time intervals for dynamic random access memories (DRAMs) 382.4.1 Introduction 382.4.2 Concepts arranged alphabeti
15、cally by symbol in each mode or cycle group 392.4.3 Concepts arranged alphabetically by symbol 422.4.4 Concepts arranged alphabetically by term 453 References 48Annex A (informative) Differences between JESD100B.01 and JESD100-B 49Index 50Figures 1 Address access time 262 Access or enable times from
16、 chip select or enable 273 Read-write cycle of a static RAM 284 Dynamic RAM addressing 305 Output disable time 316 Entering the data-retention mode 327 Leaving the data-retention mode 338 A write-read operation 359 Data valid and access time 37JEDEC Standard No. 100B.01 -iii- Foreword The purpose of
17、 this standard is to promote the uniform use of symbols, abbreviations, terms, and definitions throughout the semiconductor industry. Where applicable, reference is made to publications of the following organizations: International Electrotechnical Commission (IEC) American National Standards Instit
18、ute, Inc. (ANSI) Institute of Electrical and Electronics Engineers (IEEE) The material contained in this standard was formulated under the cognizance of JEDEC JC-10 Committee on Terms, Definitions, and Symbols and approved by the JEDEC Solid State Technology Association Board of Directors. The text
19、of this standard is based on JESD100-A, which it replaces, and the following JEDEC Board ballots: JCB-94-48, JCB-96-19, JCB-96-67, JCB-97-74, JCB-98-90, JCB-99-06, JCB-99-45, and JCB-99-49. JESD100B.01 is the first minor revision of JESD100-B, December 1999. Annex A briefly shows entries that have c
20、hanged. JEDEC Standard No. 100B.01 -iv- JEDEC Standard No. 100B.01 Page 1 TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR MICROCOMPUTERS, MICROPROCESSORS, AND MEMORY INTEGRATED CIRCUITS 1 General terms and definitions accumulator: A register in which one operand of an operation can be stored and subseque
21、ntly replaced by the result of another operation. (Ref. IEC 824.) address: (1) A character or group of characters that identifies a register, a particular part of storage, or some other data source or destination. (Ref. ANSI X3.172.) (2) To refer to a device or a data item by its address. (Ref. ANSI
22、 X3.172.) address register: A register that is used to hold an address. (Ref. IEC 824.) arithmetic and logic unit (ALU): The part of a processor that performs arithmetic operations and logic operations. (Ref. IEC 824.) arithmetic unit: The part of a processor that performs arithmetic operations. (Re
23、f. IEC 824.) NOTE This term is sometimes used for a unit that performs both arithmetic and logic operations. associative memory: Synonym for “content-addressable memory”. (Ref. IEC 748-2.) baud: A unit of signaling speed equal to the number of discrete conditions or signal events per second. (Ref. A
24、NSI X3.172.) NOTE For example, one baud equals one bit per second in a train of binary signals or one 3-bit value per second in a train of signals each of which can assume one of eight (23) different states. bit (b): (1) In the binary numeration system, either of the digits 0 or 1. (Ref. ANSI X3.172
25、.) NOTE Abbreviated form of “binary digit”. (2) The unit of storage capacity that corresponds to a single memory cell. (bit) slice: A partition of a microprocessor that enables several identical units to be paralleled or cascaded and augmented by control logic to realize the central processing unit.
26、 bit-slice processor: A central processing unit constructed of an array of identical units, each of which operates simultaneously upon one or more adjacent bits. (Ref. IEC 824.) bit-wide device: A device that has only a single-bit data interface. JEDEC Standard No. 100B.01 Page 2 1 General terms and
27、 definitions (contd) block: A continuous range of memory addresses. (Ref. IEC 748-2.) NOTE The number of addresses included in the range is frequently equal to 2n, where n is the number of bits in the address. buffer: (1) A routine or storage used to compensate for a difference in the rate of flow o
28、f data or in the time of occurrence of events, when transferring data from one device to another. (Ref. ANSI X3.172.) (2) An isolating circuit used to minimize the effects of a driven circuit on the driving circuit. (Adapted from ANSI/IEEE Std 100 and ANSI X3.172.) buffer storage: Storage used to co
29、mpensate for a difference in the rate of flow of data between components of an automatic data processing or communications system, or in the time of occurrence of events in the components. (Adapted from ANSI X3.172.) bus: A common path along which power or signals travel from one or several sources
30、to one or several destinations. (Adapted from IEC 824.) busy signal: Synonym for “wait signal” byte (B): (1) A binary character string operated upon as a unit and usually shorter than a computer word. (Ref. ANSI X3.172.) NOTE A byte is usually eight bits. (2) The unit of storage capacity equal to ei
31、ght bits. byte-wide device: A device that has a parallel data interface of eight bits, possibly with additional bits appended to provide parity or error-detection capability. cache memory: A special buffer storage, smaller and faster than main storage, that is used to hold a copy of data or instruct
32、ions that have been obtained automatically from main storage and are likely to be needed soon by the processor. (Adapted from ANSI X3.172.) NOTE It is placed between the CPU and main storage to make main storage look like fast memory. CAS latency (for an SDRAM): Synonym for “read latency”. (central)
33、 processing unit (CPU): A functional unit that consists of one or more processors and their internal storage. (Ref. ANSI X3.172.) chip-enable input: A control input that, when active, permits operation of the integrated circuit and, when inactive, causes the integrated circuit to be in a reduced-pow
34、er standby mode. (Ref. IEC 748-2.) NOTE A chip-enable input is a clock or strobe input that significantly affects the power dissipation of the integrated circuit. For example, it may be the cycle control input of a dynamic memory or a power-reduction input of a static memory. JEDEC Standard No. 100B
35、.01 Page 3 1 General terms and definitions (contd) chip-select input: A control input that, when active, permits operation of the integrated circuit and, when inactive, prevents input or output of data to or from the integrated circuit. (Ref. IEC 748-2.) clear: To preset a storage or memory device t
36、o a prescribed state, usually that denoting zero. (Ref. IEEE Std 100.) NOTE In the field of nonvolatile memories, clear conventionally means to set the outputs of the memory to the high logic level. clear algorithm (for a flash EEPROM): The timed sequence of signals necessary to clear the memory. cl
37、ear disturb: The corruption of data in one location caused by the clearing of data at another location. clock cycle: The time period, generally derived from an oscillator, that is used for sequencing data flow and synchronizing one or more functions. (Ref. IEC 824.) complex-instruction-set computer
38、(CISC): A microcomputer or microprocessor that performs multiple tasks per complex instruction, usually requiring multiple clock cycles. content-addressable memory (CAM): A memory that responds with all the data in a storage zone if a portion of that data matches the data used for addressing the mem
39、ory. (Ref. IEC 748-2.) control bus: A bus carrying the signals that regulate system operations. (Ref. ANSI X3.172.) coprocessor: A processing unit that extends the capabilities of its main processor, directly accesses the memory of that processor, and does not operate autonomously. (Ref. IEC 824.) c
40、ycle: (1) A sequence of operations in which one set of events is completed. (2) Any set of operations that is repeated regularly in the same sequence. NOTE The operations may be subject to variations on each repetition. (Ref. ANSI X3.172.) data bar polling: A method, used to determine whether the wr
41、ite operation in a memory is complete, wherein the memory is put into the read mode after initiating the write mode; if writing is complete, the outputs take on the addressed stored data, or if writing is not complete, the specified output(s) take on the complement of the last bit(s) written. NOTE I
42、f writing is not complete: (a) in older devices, normally all outputs take on the complement of the last bits written; (b) in more modern byte-wide memories, only the most significant output takes on the complement of the last bit written; (c) in word-wide memories, the most significant output of th
43、e least significant byte, the most significant output of the entire word, or both of these outputs take on the complement of the last bit written. data bus: A bus used to communicate data internally and externally to and from processing units, storage devices, or peripheral devices. (Adapted from AN
44、SI X3.172.) JEDEC Standard No. 100B.01 Page 4 1 General terms and definitions (contd) data change: An event in which at least one bit of data is caused to change. NOTE This event may be used as a unit of endurance for erasable programmable read-only memories. data cycle: A cycle in which each bit ch
45、anges to its opposite state and back to its original state. NOTE 1 These changes may occur for all bits in parallel or in series, e.g., by page, block, word, byte, or bit. NOTE 2 This cycle may be used as a unit of endurance for erasable programmable read-only memories. data-retention mode: A standb
46、y or battery mode of operation in which the integrity of stored data is maintained although the supply voltage is below that specified for reading or writing. data-retention time: Synonym for “retention time”. data rewrite: An operation including one data cycle or at least one data change, in which
47、data is written into an array. double word: A character string or binary element string that, in a given system, has twice the length of a word. duplex transmission: Data transmission in both directions simultaneously. (Ref. ANSI X3.172.) dynamic random-access memory (DRAM): A dynamic memory that pe
48、rmits access to any of its address locations in any desired sequence with similar access time to each location. dynamic (read/write) memory: A volatile read/write memory in which the cells require the repetitive application of control signals generated inside or outside the integrated circuit to ret
49、ain stored data. (Adapted from IEC 748-2.) NOTE 1 The words “read/write” may be omitted from the term when no misunderstanding is likely. NOTE 2 Each repetitive application of the control signals is normally called a refresh operation or cycle. NOTE 3 A dynamic memory can use static addressing or sensing circuits. NOTE 4 Contrast with “static (read/write) memory”. EEPROM redundancy: See “redundancy (in a memory)”. electrically erasable programmable read-only memory (EEPROM): A reprogrammable read-only memory in which the cells at each address can be erased electrically and reprogrammed
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