JEDEC JESD12-3-1986 CMOS Gate Array Macrocell Standard《CMOS门阵列宏单元标准》.pdf

1、K -. I EIA JESDLZ-3 b W 3234600 0004837 9 W JUNE 1986 JEDEC STANDARD NO. 12-3 CMOS GATE ARRAY .MACROCELL STANDARD JEDEC Solid State Products Engineering Council EIA JESDL2-3 8b 3234600 0004838 O = NOTICE This JEDEC Standard or Publication contains material that has been prepared, progressively revie

2、wed, and approved through the JEDEC Council level and subsequently reviewed and approved by the IA General Counsel. JEDEC Standards and Publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability a

3、nd improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC from manufacturing or selling products not conforming to su

4、ch standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members whether the standard is to be used either domestically or internationally. Recommended Standards are adopted by JEDEC without regard to whether or not their adoption may involve paten

5、ts or articles, materials, or processes. By such action JEDEC.does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC Standards or Publicat ions. The information included in JEDEC Standards and Publications represents a sound approa

6、ch to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC Standard, or Publication may be further processed and ultimately become an EIA Standard. Inquiries, comments, and suggestion

7、s relative to the content of this JEDEC Standard or Publication should be addressed to the JEDEC Executive Secretary at EIA Headquarters, 2001 Eye Street, N.W., Washington, D.C. 20006. Published by ELECTRONIC INDUSTRIES ASSOCIATION Engineering Department 2001 Eye Street, N.W. Washington, D.C. 20006

8、Copyright 1986 EIX“IC 1“RIES ASSOCIATION PRIE: $8.00 Printed in U.S.A. - EIA JESDL2-3 8b m 3234600 0004839 2 m / JEDEC Standard No. 12-3 CMOS GATE ARRAY MACROCELL STANDARD TABLE OF CONTENTS O 0 Paragraph 1 .o SCOPE 1.1 INTRODUCTION 1.2 RATIONAL 1.3 1 .Ir NAMING CONVENTIONS DESCRIPTION OF THE MACROCE

9、LL STANDARDS 1.5 TRUTH TABLES 1.6 FUTURE ADDITIONS . Page 1 1 1 2 2 3 3 2.0 JEDEC STANDARD CMOS GATE ARRAY MACROCELLS 4 - 13 _- .Y _I , f Y EIA JESDL2-3 86 m 3234600 0004840 9 m JEDEC Standard No. 12-3 Page 1 CMOS GATE ARRAY MACROCELL STANDARD (From JEDEC Council Ballot JCB-85-16, formulated under t

10、he cognizance of 32-44.1 Committee on Gate Arrays.) I 1.0 SCOPE 1.1 INTRODUCTION This JEDEC Standard defines a minimum set of macrocell standards for CMOS gate arrays. A total of 41 macrocell types are addressed, all of which are commonly used by gate array designers to implement Application Specifi

11、c Integrated Circuits. The logic types covered include: NAND NOR XOR/XNOR INVERTERS MULTIPLEXER 1/0 INTERFACE LATCHES FLIP FLOPS AND/OR/INVERT 1.2 RATIONALE With the advent of Computer Aided Design Tools on minicomputers and workstations, a number of gate array users are now doing logic netlist defi

12、nition and functional simulation on inhouse machines in order to optimize development time and costs. Once a correct functional simulation is obtained, the user is then ready ta transfer his design to a specific gate array vendor. However, unless come minimum set of commonly accepted macrocells exis

13、ts in the industry, it is entirely possible that the user may configure his logic in cells that may not be directly translatable to cells in the vendors library. As such, duplication of efforts and extra time spent on transferring a specific design to a vendor often happens, which affects the final

14、cost to the user, Alternatively, a user may want to configure his logic in advance of choosing a vendor and yet be able to map his logic over to several vendors libraries of cells with minimum difficulty. While CAD standards efforts such as EDIF address issues of translation of netlists between unli

15、ke CAD systems, they do not cover standard macrocell types. Hence, this Standard is meant to facilitate easy netlist transfer between vendors and users. . EIA JESDL2-3 8b m 3234b00 000484L O m JEDEC Standard No. 12-3 Page 2 1.3 DESCRIPTION OF THE MACROCELL STANDARDS: Each macrocell in this standard

16、is described by the following information: MACROCELL NAME LOGIC SYMBOL TRUTH TABLE JEDEC NETLIST DEFINITION AND DESCRIPTION This information gives a complete functional description of the macrocell for purposes of incorporating it into a CAD environment to capture netlists and perform functional sim

17、ulation. specific details such as AC performance, transistor intercon- nections, gates used per macrocell type, temperature degradation of performance, process implementation and design rules are not within the scope of this ballot and are therefore not covered. user would be expected to obtain this

18、 information directly from his vendor of choice at the time of design implementation. Vendar A 1.4 NAMING CONVENTIONS: Naming conventions are always a subject of high concern among semicustom XC designers. The following convention has been used successfully by several companies and is known to work

19、in the semicustom IC marketplace. macrocell standards is JXXXXXXn where the following rules were used in arriving at this convention: - Up to 8 fields may be used to define a macrocell name. name length will be kept to the minimum required to adequately name the macrocell. - The first character used

20、 will be a J to denote a JEDEC macrocell. The basic format for naming the The 7 EIA JESDL2-3 86 = 3234600 0004842 2 JEDEC Standard No. 12-3 Page 3 - The next letters (up to six) will be used to describe the type of macrocell. Experience has shown us that logic designers prefer names that are somewha

21、t descriptive of the logic type. Since this standard deals with a limited number of macrocell types, it makes such a convention possible. Thus, for example: ND = NR = xo = IV = AO1 = BI = BTB = BIS = BIT = BIC = BO = BTO = Mx= LD = LDR = LDS = FJKR = FDSR = FDR = FDS = FJKS = PSS = PDD = NAND NOR EX

22、CLUSIVE OR INVERTER AND OR INVERT BUFFER INPUT BUFFER THREE-STATE BIDIRECTIONAL SCHMITT TRIGGER INPUT BUFFER TTL INPUT BUFFER CMOS INPUT BUFFER OUTPUT BUFFER THREE-STATE OUTPUT BUFFER MULTIPLEXER D TYPE LATCH D LATCH WITH ACTIVE LOW RESET D LATCH WITH ACTIVE LOW SET JK FLIP FLOP WITH ACTIVE LOW RESE

23、T D TYPE FLIP FLOP WITH ACTIVE LOW SET AND ACTIVE LOW RESET D FLIP FLOP WITH ACTIVE LOW RESET D FLIP FLOP WITH ACTIVE LOW.SET JK FLIP FLOP WITH ACTIVE LOW SET Vss PAD VDD PAD - Every macrocell name will conclude with a numeric. This permits several variations of the same macrocell type without chang

24、ing the basic macrocell name. Thus, for,example: JIV1 = INVERTER JIV3 = 3 X POWER INVERTER JMXZ = 2:l MULTIPLEXER JMX4 = 4:l MULTIPLEXER JBIT1 = BUFFER WITH TTL INPUTS JBITZ = BUF-FER WITH TTL INPUTS 4 PULL UP, etc. 1.5 TRUTH TABLES: All Truth tables are specified in positive logic using the notatio

25、n 1 = HIGH, O TRANSITION, Z = HIGH IMPEDANCE. LOW, U = UNDEFINED, X = DONT CARE,* = LOW TO HIGH 1.6 FUTURE ADDITIONS: New macrocell types and names will be added to this list period- ically by JC-44 as it becomes necessary to do so. EIA JESD12-3 6 9 3234600 0004843 4 9 JEDEC Standard No. 12-3 Page 4

26、 2.0 JEDEC STANDARD CMOS GATE,ARRAY MACROCELLS NAND GATES - IACRC :ELL JAME_ IND2 - IND 3 - JND4 - JND6 - JND8 - LOGIC SYMBOL B eDY. C A4 D F-l E G . TRU,TH TABLE A B % 11 o 10 1 o1 1 O0 1 ABC y 111 o xxo 1 xox 1 oxx 1. AB C D Y 1111 o xxxo 1 xxox 1 xoxx 1 oxxx 1 ABCDEF Y 111111 o xxxxxo 1 xxxxox 1

27、xxxoxx 1 xxoxxx 1 xoxxxx 1 oxxxxx 1 ABCDEFGH Y 11111111 o xxxxxxxo 1 xxxxxxox 1 xxxxxoxx 1 xxxxoxxx 1 xxxoxxxx 1 xxoxxxxx 1 xoxxxxxx 1 oxxxxxxx 1 IEDEC NETLIST DEFINITION LND DESCRIPTION . PJND2 (A,B) . 2-INPUT NAND 3-INPUT NAND . PIJND4 (A, B , C , D) 4-INPUT NAND TT=JND6 (A, B, c, D, E F) 6-INPUT

28、NANP Y.JND8 (A, B, C ,D ,-E, F ,G, H) 8-INPUT NAND % EIA JESDL2-3 86 3234600 0004844 b JEDEC NETLIST DEFINITION MAGRQ CELL, LOGIC SYMBOL TRUTH TABLE AND DESCRIPTION NAdG JNR2 AB Y xJNR2 (A,B) O0 1 10 o ,B o1 o 2-INPUT NOR “Dy 11 o JNR3 ABC Y YJNR3 (A,B,C) O00 1 1xx o xx1 o BSY. x1x o 3-INPUT NOR C J

29、NR4 ABCD Y. Y“JNR4 (A,B,C,D) O000 1 IXXX o XlXX o 4-INPUT NOR D xx1x o xxx1 o e JEDEC Standard No. 12-3 Page 5 JEDEC STANDARD CMOS GATE ARRAY MACROCELLS (CONTD.) b NOR GATES O . EIA JESDLZ-3 86 = 3234600 0004845 JEDEC Standard No. 12-3 Page 6 JEDEC STANDARD- CMOS GATE ARRAY MACROCELLS (CONTD.) EXCLU

30、SIVE OR/NOR MACRO CELL NAXE JXO2 JXN2 LOGIC SYMBOL TRUTH TABLE 4.B y 11 o 10 1 o1 1 O0 o AB y 11 1 10 o O0 1 o 1, o JEDEC NETLIST DEFINITION AND DESCRIPTION 2-INPUT EXCLUSIVE- OR YJXN2 (A,B) 2-INPUT EXCLUSIVE NOR t. EIA JESDL2-3 86 3234600 000Li84b T JEDEC Standard No. 12-3 Page 7 JEDEC STANDARD CMO

31、S GATE ARRAY MACROCELLS (CONTD.). AND/OR COMBINATION IIACRO ZELL 9 A?! 3 JA011 JA012 1 JOAI 1 JOA12 LOG1 C SYMBOL C C D D cay TRUTH TABLE ABCD 1 11xx o xx11 o oxox 1 xoox 1 oxxo 1 xoxo 1 ABCD y 1-1xx o AXIX.O xxx1 o xooo 1 ox00 1 ABCD Y 1x11 o x111 o OOAX 1 xxox 1 xxxo 1 ABCD y ooxx 1 xxoo 1 1XlX o

32、x11x o 1xx1 o XlX1 o JEDEC NETLIST DEFINITION AND DESCRIPTION YJAOI1 (A,B,C,D) 2x2 INPUT AND INTO 2 INPUT NOR YJAOI2 (A,B,C,D) 2 INPUT AND INTO 3 INPUT NOR Y-JOAI1 (A,B,C,D) 2 INPUT OR INTO 3 INPUT NAND y-JOA12 (A,B,C,D) 2x2 INPUT OR INTO 2 INPUT NAND EIA JESDL2-3 b 3234600 0004847 L JEDEC Standard

33、No. 12-3 Page 8 JEDEC STANDARD CMOS GATE ARRAY MACROCELLS (CONTID.) INVERTERS dACRO :ELL gAME JIV1 JIV2 JIV3 JIV4 LOGIC SYMBOL Amy Y *a Y .A TRUTH TABLE A Y 1 O O 1 A Y 1 O O 1 A Y 1 O O 1; A Y .1 O O 1 JEDEC NETLIST DEFlN.IT/ON AND DESCRIPTION INVERTER YnJIV2 (A) 2X POWER INVERTER Y-JIV3 (A) 3X POW

34、ER INVERTER Y-JIVQ (A) 4X POWER INVERTER EIA JESD12-3 86 3234b00 0004848 3 m JEDEC Standard No. 12-3 Page 9 JEDEC .STANDARD CMOS GATE ARRAY. MACROCELLS (CONTI D. $ 1/0 INTERFACE TRUTH TABLE JEDEC NETLIST DEFINITION AND DESCRIPTION MACRO CELL NAME JBIS1 LOGIC SYMBOL Y.=JBISl (A) SCHMITT TRIGGER INPUT

35、 BUFFER A Y O O 1 1 . JBIT1 YJBIT1 (A) TTL INPUT BUFFER A Y O O 1 1 JBIC1 Y=JBICl (A) CMOS INPUT BUFFER A Y O O 1 1 yn=JBIC2 (A) JBIC2 JDIT2 A Y O O 1 1 Z 1 CMOS INPUT BUFFER WITH PULL UP Y=JBIT2 (A) A Y O O 1 1 x 1 TTL INPUT BUFFER WITH PULL UP JBQ1 .y=JBOl (A) A Y O O 1 1 OUTPUT BUFFER iTDD G!bU Y

36、 JB02 Y,=JBo2 (AN) AN y O 1 1 2 OPEN DRAIN OUTPUT BUFFER WITH P CHANNEL PULL UP Y=JB03 (AN) JB03 OPEN DRAIN OUTPUT BUFFER WITH N CHANHEL PULL DOWN EIA JESD12-3 86 3234b00 0004849 5 JEDEC Standard No. 12-3 Page 10 JEIDEO. STANDARD CMOS GATE .ARRAY MACROCELLS (CONTID. I/O INTERFACE (CONTI MACRO CELL N

37、AME JBTO1 JBTB1 JBTB2 LOGIC SYMBOL EN-? Vss/VDD PADS JPSS1 JPDD1 6” TRUTH TABLE JEDEC NETLEST DEFINITION AND DESCRIPTION Y =JBTOl (A,EN) A EN Y O0 o 10 1 3 STATE OUTPUT BUFFER x1 z I AENYB O0 O0 YJBTB1 (A,EN) I 10 11. 3 STATE 1/0 BUFFER x1 zz AENYB O0 O0 io ii x1 11 YJBTB2 (A,EN) 3 STATE 1/0 BUFFER

38、WITH PULL UP I vss FAD I I I I PAD I DD EIA JESDL2-3 6 m 3234600 0004850 L m JEDEC Standard No. 12-3 Page dl JEDEC STANDARD CMOS GATE ARRAY MACROCELLS (CONTID.) * MULTIPLEXER EIA JESDL2-3 b 3234600 O004853 3 MACRO CELL NAME LOGIC SYMBOL .TRUTH TABLE . JEDEC Standard No. 12-3 Page 12 JEDEC STANDARD C

39、MOS GATE ARRAY MACROCELLS (CONTID. JEDEC NETLIST DEFINITION AND DESCRIPTION X 11 Q QN O010 1 1011 o JLDR1 D LATCH WITH ACTIVE LOW RESET .D 0410 1 l+ll o X O1 Q QN z (Q,QN)-JLDR (D,GN,RN) I D GN RN Q QN xxoo 1 D FLIP FLOP WIT8 ACTIVk LOW RESET . . D CP SN Q QN x xo1 o o +lo 1 1411 o I O1 Q QN JLDS 1

40、z (Q,QN)-JFDSI (D,CP,SN) D FLIP FLOP WITH ACTIVE LOW SET z (Q,QN)=JLDSI (D,GN,SN) I D G.N SN Q QN xxo1 o xxo110 0.41 1 o 1 141110 xxoouu X Il Q QN O010 1 I D LATCH WXTH ACTIVE D FLIP FLOP WITH ACTIVE LOW SET AND ACTIVE LOW RESET 1 O 1 1 O I LOW SET I I 1 I D FLIP FLOP JFDR1 I , JFDS1 I I I JFDSR1 I

41、D CP RN Q QN I z (Q,QN)=JFDR (D,CP,RN) x xo o 1. Z (Q,QN)=JFDSRl xx1001 * - EIA JESD12-3 86 3234600 ROO4852 5 M JEDEC Standard No. 12-3 Page 13 JEDEC STANDARD CMOS GATE ARRAY MACROCELLS (CONTD.) e JK FLIP FLOP MACRO CELL NAME JFJKR1 JFJRS1 LOGIC SYMBOL TRUTH TABLE J K CP RN Q QN xx xo o 1 10 61 1 o o1 41 o 1 O0 41 QQN 11.elQN Q J K CP SN Q QN xx xo 1 o 10 41 1 o o1 410 1 O0 61 QQN 11 6lQN Q JEDEC NETLIST DEFINITION AND DESCRIPTION z (Q,QN)=JFJKR . (J,K,CP,RN) JK FLIP FLOP WITH ACTIVE LOW RESET z (Q,QN)=JFJKS (J,X,CP,SN) JK FLIP FLOP WITH ACTIVE LOW SET